EFM32WG Datasheet, PDF (296/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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3. In Slave mode, when isochronous OUT endpoints are supported in the device, the application must
read all isochronous OUT data packets from the receive FIFO (data and status) before the end of
the periodic frame (USB_GINTSTS.EOPF interrupt). In DMA mode, the application must guarantee
enough bandwidth to allow emptying the isochronous OUT data packet from the receive FIFO before
the end of each periodic frame.
4. To receive data in the following frame, an isochronous OUT endpoint must be enabled after the
USB_GINTSTS.EOPF and before the USB_GINTSTS.SOF.
Internal Data Flow
1. The internal data flow for isochronous OUT endpoints is the same as that for non-isochronous OUT
endpoints, but for a few differences.
2. When an isochronous OUT endpoint is enabled by setting the Endpoint Enable and clearing the NAK
bits, the Even/Odd frame bit must also be set appropriately. The core receives data on a isochronous
OUT endpoint in a particular frame only if the following condition is met.
• USB_DOEPx_CTL.DPIDEOF (Even/Odd frame) = USB_DSTS.SOFFN[0]
3. When either the application or the internal DMA completely reads an isochronous OUT data packet
(data and status) from the receive FIFO, the core updates the USB_DOEPx_TSIZ.RXDPIDSUPCNT
(Received DPID) field with the data PID of the last isochronous OUT data packet read from the receive
FIFO.
Application Programming Sequence
1. Program the USB_DOEPx_TSIZ register for the transfer size and the corresponding packet count.
When in DMA mode, also program the USB_DOEPx_DMAADDR register.
2. Program the USB_DOEPx_CTL register with the endpoint characteristics and set the Endpoint
Enable, ClearNAK, and Even/Odd frame bits.
• Endpoint Enable = 1
• CNAK = 1
• Even/Odd frame = (0: Even/1: Odd)
1. In Slave mode, wait for the USB_GINTSTS.Rx StsQ level interrupt and empty the data packets from
the receive FIFO as explained in Packet Read from FIFO in Slave Mode (p. 290) .
• This step can be repeated many times, depending on the transfer size.
1. The assertion of the USB_DOEPx_INT.XFERCOMPL interrupt marks the completion of the
isochronous OUT data transfer. This interrupt does not necessarily mean that the data in memory
is good.
2. This interrupt can not always be detected for isochronous OUT transfers. Instead, the application can
detect the USB_GINTSTS.INCOMPLP (Incomplete Isochronous OUT data) interrupt. See Incomplete
Isochronous OUT Data Transfers in DMA and Slave Modes (p. 301) , for more details
3. Read the USB_DOEPx_TSIZ register to determine the size of the received transfer and to determine
the validity of the data received in the frame. The application must treat the data received in memory
as valid only if one of the following conditions is met.
• USB_DOEPx_TSIZ.RXDPID = D0 and the number of USB packets in which this payload was
received = 1
• USB_DOEPx_TSIZ.RXDPID = D1 and the number of USB packets in which this payload was
received = 2
• USB_DOEPx_TSIZ.RXDPID = D2 and the number of USB packets in which this payload was
received = 3
• The number of USB packets in which this payload was received = App Programmed Initial Packet
Count – Core Updated Final Packet Count
The application can discard invalid data packets.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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