EFM32WG Datasheet, PDF (51/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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• A channel select block routing the right peripheral request to each DMA channel
8.4 Functional Description
The DMA Controller is highly flexible. It is capable of transferring data between peripherals and memory
without involvement from the processor core. This can be used to increase system performance by
off-loading the processor from copying large amounts of data or avoiding frequent interrupts to service
peripherals needing more data or having available data. It can also be used to reduce the system energy
consumption by making the DMA work autonomously with the LEUART for data transfer in EM2 without
having to wake up the processor core from sleep.
The DMA Controller contains 12 independent channels. Each of these channels can be connected to any
of the available peripheral trigger sources by writing to the configuration registers, see Section 8.4.1 (p.
51) . In addition, each channel can be triggered by software (for large memory transfers or for
debugging purposes).
What the DMA Controller should do (when one of its channels is triggered) is configured through channel
descriptors residing in system memory. Before enabling a channel, the software must therefore take
care to write this configuration to memory. When a channel is triggered, the DMA Controller will first read
the channel descriptor from system memory, and then it will proceed to perform the memory transfers
as specified by the descriptor. The descriptor contains the memory address to read from, the memory
address to write to, the number of bytes to be transferred, etc. The channel descriptor is described in
detail in Section 8.4.3 (p. 62) .
In addition to the basic transfer mode, the DMA Controller also supports two advanced transfer modes;
ping-pong and scatter-gather. Ping-pong transfers are ideally suited for streaming data for high-speed
peripheral communication as the DMA will be ready to retrieve the next incoming data bytes immediately
while the processor core is still processing the previous ones (and similarly for outgoing communication).
Scatter-gather involves executing a series of tasks from memory and allows sophisticated schemes to
be implemented by software.
Using different priority levels for the channels and setting the number of bytes after which the DMA
Controller re-arbitrates, it is possible to ensure that timing-critical transfers are serviced on time.
8.4.1 Channel Select Configuration
The channel select block allows selecting which peripheral's request lines (dma_req, dma_sreq) to
connect to each DMA channel.
This configuration is done by software through the control registers DMA_CH0_CTRL-
DMA_CH11_CTRL, with SOURCESEL and SIGSEL components. SOURCESEL selects which
peripheral to listen to and SIGSEL picks which output signals to use from the selected peripheral.
All peripherals are connected to dma_req. When this signal is triggered, the DMA performs a number
of transfers as specified by the channel descriptor (2^R). The USARTs are additionally connected to the
dma_sreq line. When only dma_sreq is asserted but not dma_req, then the DMA will perform exactly
one transfer only (given that dma_sreq is enabled by software).
8.4.2 DMA control
8.4.2.1 DMA arbitration rate
You can configure when the controller arbitrates during a DMA transfer. This enables you to reduce the
latency to service a higher priority channel.
The controller provides four bits that configure how many AHB bus transfers occur before it re-arbitrates.
These bits are known as the R_power bits because the value you enter, R, is raised to the power of two
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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