EFM32WG Datasheet, PDF (168/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Bit
Name
Reset
Access Description
1
CH1PULSE
0
W1
Channel 1 Pulse Generation
See bit 0.
0
CH0PULSE
0
W1
Channel 0 Pulse Generation
Write to 1 to generate one HFPERCLK cycle high pulse. This pulse is XOR'ed with the corresponding bit in the SWLEVEL register
and the selected PRS input signal to generate the channel output.
13.5.2 PRS_SWLEVEL - Software Level Register
Offset
0x004
Reset
Access
Bit Position
Name
Bit
31:12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
CH11LEVEL
0
RW
Channel 11 Software Level
See bit 0.
CH10LEVEL
0
RW
Channel 10 Software Level
See bit 0.
CH9LEVEL
0
RW
Channel 9 Software Level
See bit 0.
CH8LEVEL
0
RW
Channel 8 Software Level
See bit 0.
CH7LEVEL
0
RW
Channel 7 Software Level
See bit 0.
CH6LEVEL
0
RW
Channel 6 Software Level
See bit 0.
CH5LEVEL
0
RW
Channel 5 Software Level
See bit 0.
CH4LEVEL
0
RW
Channel 4 Software Level
See bit 0.
CH3LEVEL
0
RW
Channel 3 Software Level
See bit 0.
CH2LEVEL
0
RW
Channel 2 Software Level
See bit 0.
CH1LEVEL
0
RW
Channel 1 Software Level
See bit 0.
CH0LEVEL
0
RW
Channel 0 Software Level
The value in this register is XOR'ed with the corresponding bit in the SWPULSE register and the selected PRS input signal to generate
the channel output.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
168
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