EFM32WG Datasheet, PDF (354/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

Offset
0x3C004
Reset
Access
Name
...the world's most energy friendly microcontrollers
Bit Position
Bit
31:20
19
18
17
16:10
9
8
7:3
2
1:0
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
DBNCEDONE
0
RW1
Debounce Done (host only)
The core sets this bit when the debounce is completed after the device connect. The application can start driving USB reset after
seeing this interrupt. This bit is only valid when the HNP Capable or SRP Capable bit is set in the Core USB Configuration register
(USB_GUSBCFG.HNPCAP or USB_GUSBCFG.SRPCAP, respectively). This bit can be set only by the core and the application
should write 1 to clear it.
ADEVTOUTCHG
0
RW1
A-Device Timeout Change (host and device)
The core sets this bit to indicate that the A-device has timed out while waiting for the B-device to connect. This bit can be set only
by the core and the application should write 1 to clear it.
HSTNEGDET
0
RW1
Host Negotiation Detected (host and device)
The core sets this bit when it detects a host negotiation request on the USB. This bit can be set only by the core and the application
should write 1 to clear it.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
HSTNEGSUCSTSCHNG 0
RW1
Host Negotiation Success Status Change (host and device)
The core sets this bit on the success or failure of a USB host negotiation request. The application must read the Host Negotiation
Success bit of the OTG Control and Status register (USB_GOTGCTL.HSTNEGSCS) to check for success or failure. This bit can be
set only by the core and the application should write 1 to clear it.
SESREQSUCSTSCHNG 0
RW1
Session Request Success Status Change (host and device)
The core sets this bit on the success or failure of a session request. The application must read the Session Request Success bit
in the OTG Control and Status register (USB_GOTGCTL.SESREQSCS) to check for success or failure. This bit can be set only by
the core and the application should write 1 to clear it.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
SESENDDET
0
RW1
Session End Detected (host and device)
The core sets this bit when VBUS is in the range 0.8V - 2.0V. This bit can be set only by the core and the application should write
1 to clear it.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
15.6.10 USB_GAHBCFG - AHB Configuration Register
This register can be used to configure the core after power-on or a change in mode. This register
mainly contains AHB system-related configuration parameters. Do not change this register after the
initial programming. The application must program this register before starting any transactions on either
the AHB or the USB.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
354
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