EFM32WG Datasheet, PDF (570/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

Bit
11
10:8
7:5
4
3
2
1:0
...the world's most energy friendly microcontrollers
Name
Value
1
2
3
Reset
Mode
LFRCO
LFXO
ULFRCO
Access Description
Description
LFRCO selected as BURTC clock source.
LFXO selected as BURTC clock source.
ULFRCO selected as BURTC clock source.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
PRESC
0x0
RW
The BURTC will be prescaled by a factor of 2^PRESC
Select BURTC prescaler factor
Value
0
1
2
3
4
5
6
7
Mode
DIV1
DIV2
DIV4
DIV8
DIV16
DIV32
DIV64
DIV128
Description
No prescaling.
Prescaling factor of 2
Prescaling factor of 4
Prescaling factor of 8
Prescaling factor of 16
Prescaling factor of 32
Prescaling factor of 64
Prescaling factor of 128
LPCOMP
0x0
RW
Low power mode compare configuration
This bit-field configures which bits to be evaluated for compare match in low power mode.
Value
0
1
2
3
4
5
6
7
Mode
IGN0LSB
IGN1LSB
IGN2LSB
IGN3LSB
IGN4LSB
IGN5LSB
IGN6LSB
IGN7LSB
Description
Do not ignore any bits for compare match evaluation.
The LSB of the counter is ignored for compare match evaluation.
The two LSBs of the counter are ignored for compare match evaluation.
The three LSBs of the counter are ignored for compare match evaluation.
The four LSBs of the counter are ignored for compare match evaluation.
The five LSBs of the counter are ignored for compare match evaluation.
The six LSBs of the counter are ignored for compare match evaluation.
The seven LSBs of the counter are ignored for compare match evaluation.
COMP0TOP
0
RW
Compare clear enable
When set, the counter wraps around when CNT equals COMP0
RSTEN
1
RW
Enable BURTC reset
Reset the Backup RTC. Register values are not reset.
DEBUGRUN
0
RW
Debug Mode Run Enable
Set this bit to keep the BURTC running during a debug halt.
Value
0
1
Description
RTC is frozen in debug mode
RTC is running in debug mode
MODE
0x0
RW
BURTC Enable
Configure in which energy modes the BURTC should keep running.
Value
0
1
2
3
Mode
DISABLE
EM2EN
EM3EN
EM4EN
Description
The BURTC is disabled.
The BURTC is in normal operating mode, operating in EM0-EM2. Oscillators must be
enabled in CMU for use.
The BURTC is enabled in EM0-EM3. Will prevent CMU from disabling used oscillators
all the way down to EM3.
The BURTC is enabled in EM0-EM4. Will prevent CMU from disabling used oscillators
all the way down to EM4.
22.5.2 BURTC_LPMODE - Low power mode configuration (Async Reg)
For more information about Asynchronous Registers please see Section 5.3 (p. 21) .
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
570
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