EFM32WG Datasheet, PDF (253/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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1. Program the USB_GINTMSK register to unmask the following:
2. Channel Interrupt
• Non-periodic Transmit FIFO Empty for OUT transactions (applicable for Slave mode that operates
in pipelined transaction-level with the Packet Count field programmed with more than one).
• Non-periodic Transmit FIFO Half-Empty for OUT transactions (applicable for Slave mode that
operates in pipelined transaction-level with the Packet Count field programmed with more than one).
3. Program the USB_USB_HAINTMSK register to unmask the selected channels’ interrupts.
4. Program the HCINTMSK register to unmask the transaction-related interrupts of interest given in the
Host Channel Interrupt register.
5. Program the selected channel’s USB_HCx_TSIZ register.
Program the register with the total transfer size, in bytes, and the expected number of packets,
including short packets. The application must program the PID field with the initial data PID (to be
used on the first OUT transaction or to be expected from the first IN transaction).
6. Program the selected channels’ USB_HCx_DMAADDR register(s) with the buffer start address (DMA
mode only).
7. Program the USB_HCx_CHAR register of the selected channel with the device’s endpoint
characteristics, such as type, speed, direction, and so forth. (The channel can be enabled by setting
the Channel Enable bit to 1 only when the application is ready to transmit or receive any packet).
Repeat the above steps for other channels.
Note
De-allocate channel means after the transfer has completed, the channel is disabled. When
the application is ready to start the next transfer, the application re-initializes the channel by
following these steps.
15.4.3.2 Halting a Channel
The application can disable any channel by programming the USB_HCx_CHAR register with the
USB_HCx_CHAR.CHDIS and USB_HCx_CHAR.CHENA bits set to 1. This enables the host to flush
the posted requests (if any) and generates a Channel Halted interrupt. The application must wait for the
USB_HCx_INT.CHHLTD interrupt before reallocating the channel for other transactions. The host does
not interrupt the transaction that has been already started on USB.
In Slave mode operation, before disabling a channel, the application must ensure that there is at
least one free space available in the Non-periodic Request Queue (when disabling a non-periodic
channel) or the Periodic Request Queue (when disabling a periodic channel). The application can
simply flush the posted requests when the Request queue is full (before disabling the channel), by
programming the USB_HCx_CHAR register with the USB_HCx_CHAR.CHDIS bit set to 1, and the
USB_HCx_CHAR.CHENA bit reset to 0.
The core generates a RXFLVL interrupt when there is an entry in the queue. The application must read/
pop the USB_GRXSTSP register to generate the Channel Halted interrupt.
To disable a channel in DMA mode operation, the application need not check for space in the Request
queue. The host checks for space in which to write the Disable request on the disabled channel’s
turn during arbitration. Meanwhile, all posted requests are dropped from the Request queue when the
USB_HCx_CHAR.CHDIS bit is set to 1.
The application is expected to disable a channel under any of the following conditions:
1. When a USB_HCx_INT.XFERCOMPL interrupt is received during a non-periodic IN transfer or high-
bandwidth interrupt IN transfer (Slave mode only)
2. When a USB_HCx_INT.STALL, USB_HCx_INT.XACTERR, USB_HCx_INT.BBLERR, or
USB_HCx_INT.DATATGLERR interrupt is received for an IN or OUT channel (Slave mode only).
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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