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EFM32WG Datasheet, PDF (345/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.
15.5 Register Map
...the world's most energy friendly microcontrollers
The offset register address is relative to the registers base address.
Offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x3C000
0x3C004
0x3C008
0x3C00C
0x3C010
0x3C014
0x3C018
0x3C01C
0x3C020
0x3C024
0x3C028
0x3C02C
0x3C05C
0x3C100
0x3C104
0x3C108
0x3C10C
0x3C110
0x3C114
0x3C118
0x3C400
0x3C404
0x3C408
0x3C410
0x3C414
0x3C418
0x3C440
0x3C500
0x3C508
0x3C50C
0x3C510
0x3C514
...
Name
USB_CTRL
USB_STATUS
USB_IF
USB_IFS
USB_IFC
USB_IEN
USB_ROUTE
USB_GOTGCTL
USB_GOTGINT
USB_GAHBCFG
USB_GUSBCFG
USB_GRSTCTL
USB_GINTSTS
USB_GINTMSK
USB_GRXSTSR
USB_GRXSTSP
USB_GRXFSIZ
USB_GNPTXFSIZ
USB_GNPTXSTS
USB_GDFIFOCFG
USB_HPTXFSIZ
USB_DIEPTXF1
USB_DIEPTXF2
USB_DIEPTXF3
USB_DIEPTXF4
USB_DIEPTXF5
USB_DIEPTXF6
USB_HCFG
USB_HFIR
USB_HFNUM
USB_HPTXSTS
USB_HAINT
USB_HAINTMSK
USB_HPRT
USB_HC0_CHAR
USB_HC0_INT
USB_HC0_INTMSK
USB_HC0_TSIZ
USB_HC0_DMAADDR
USB_HCx_CHAR
Type
RW
R
R
W1
W1
RW
RW
RWH
RW1
RW
RWH
RWH
RWH
RW
R
R
RW
RW
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
R
R
RW
RWH
RW
RW1
RW
RW
RW
RW
Description
System Control Register
System Status Register
Interrupt Flag Register
Interrupt Flag Set Register
Interrupt Flag Clear Register
Interrupt Enable Register
I/O Routing Register
OTG Control and Status Register
OTG Interrupt Register
AHB Configuration Register
USB Configuration Register
Reset Register
Interrupt Register
Interrupt Mask Register
Receive Status Debug Read Register
Receive Status Read and Pop Register
Receive FIFO Size Register
Non-periodic Transmit FIFO Size Register
Non-periodic Transmit FIFO/Queue Status Register
Global DFIFO Configuration Register
Host Periodic Transmit FIFO Size Register
Device IN Endpoint Transmit FIFO 1 Size Register
Device IN Endpoint Transmit FIFO 2 Size Register
Device IN Endpoint Transmit FIFO 3 Size Register
Device IN Endpoint Transmit FIFO 4 Size Register
Device IN Endpoint Transmit FIFO 5 Size Register
Device IN Endpoint Transmit FIFO 6 Size Register
Host Configuration Register
Host Frame Interval Register
Host Frame Number/Frame Time Remaining Register
Host Periodic Transmit FIFO/Queue Status Register
Host All Channels Interrupt Register
Host All Channels Interrupt Mask Register
Host Port Control and Status Register
Host Channel x Characteristics Register
Host Channel x Interrupt Register
Host Channel x Interrupt Mask Register
Host Channel x Transfer Size Register
Host Channel x DMA Address Register
Host Channel x Characteristics Register
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
345
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