EFM32WG Datasheet, PDF (356/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Bit
Name
Reset
Access Description
Value
0
1
3
5
7
Mode
SINGLE
INCR
INCR4
INCR8
INCR16
Description
Single transfer.
Incrementing burst of unspecified length.
4-beat incrementing burst.
8-beat incrementing burst.
16-beat incrementing burst.
0
GLBLINTRMSK
0
RW
Global Interrupt Mask (host and device)
The application uses this bit to mask or unmask the interrupt line assertion to itself. Irrespective of this bit's setting, the interrupt status
registers are updated by the core. Set to unmask.
15.6.11 USB_GUSBCFG - USB Configuration Register
This register can be used to configure the core after power-on or a changing to Host mode or Device
mode. It contains USB and USB-PHY related configuration parameters. The application must program
this register before starting any transactions on either the AHB or the USB. Do not make changes to
this register after the initial programming.
Offset
0x3C00C
Reset
Access
Bit Position
Name
Bit
31
30
29
28
27:23
22
21:14
13:10
Name
Reset
Access Description
CORRUPTTXPKT
0
W1
Corrupt Tx packet (host and device)
This bit is for debug purposes only. Never Set this bit to 1. The application should always write 0 to this bit.
FORCEDEVMODE
0
RW
Force Device Mode (host and device)
Writing a 1 to this bit forces the core to device mode irrespective of the state of the ID pin. After setting the force bit, the application
must wait at least 25 ms before the change to take effect.
FORCEHSTMODE
0
RW
Force Host Mode (host and device)
Writing a 1 to this bit forces the core to host mode irrespective of the state of the ID pin. After setting the force bit, the application
must wait at least 65 ms before the change to take effect.
TXENDDELAY
0
RW
Tx End Delay (device only)
Writing 1 to this bit enables the core to follow the TxEndDelay timings as per UTMI+ specification 1.05 section 4.1.5 for opmode
signal during remote wakeup.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
TERMSELDLPULSE
0
RW
TermSel DLine Pulsing Selection (device only)
This bit selects utmi_termselect to drive data line pulse during SRP.
Value
0
1
Mode
TXVALID
TERMSEL
Description
Data line pulsing using utmi_txvalid.
Data line pulsing using utmi_termsel.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
USBTRDTIM
0x5
RW
USB Turnaround Time (device only)
Sets the turnaround time in PHY clocks. Specifies the response time For a MAC request to the Packet FIFO Controller (PFC) to fetch
data from the DFIFO (SPRAM). Always write this field to 5.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
356
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