EFM32WG Datasheet, PDF (288/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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15.4.4.2.2.1 Control Write Transfers (SETUP, Data OUT, Status IN)
This section describes control write transfers.
Application Programming Sequence
1. Assertion of the USB_DOEPx_INT.SETUP Packet interrupt indicates that a valid SETUP packet
has been transferred to the application. See OUT Data Transfers in Slave and DMA Modes (p.
285) for more details. At the end of the Setup stage, the application must reprogram the
USB_DOEPx_TSIZ.SUPCNT field to 3 to receive the next SETUP packet.
2. If the last SETUP packet received before the assertion of the SETUP interrupt indicates a data OUT
phase, program the core to perform a control OUT transfer as explained in Generic Non-Isochronous
OUT Data Transfers Without Thresholding in DMA and Slave Modes (p. 293) .
In DMA mode, the application must reprogram the USB_DOEPx_DMAADDR register to receive a
control OUT data packet to a different memory location.
3. In a single OUT data transfer on control endpoint 0, the application can receive up to 64 bytes. If the
application is expecting more than 64 bytes in the Data OUT stage, the application must re-enable
the endpoint to receive another 64 bytes, and must continue to do so until it has received all the data
in the Data stage.
4. Assertion of the USB_DOEPx_INT.Transfer Completed interrupt on the last data OUT transfer
indicates the completion of the data OUT phase of the control transfer.
5. On completion of the data OUT phase, the application must do the following.
• To transfer a new SETUP packet in DMA mode, the application must re-enable the control OUT
endpoint as explained in OUT Data Transfers in Slave and DMA Modes (p. 285) .
• USB_DOEPx_CTL.EPENA = 1
• To execute the received Setup command, the application must program the required registers in
the core. This step is optional, based on the type of Setup command received.
6. For the status IN phase, the application must program the core as described in Generic Non-Periodic
(Bulk and Control) IN Data Transfers Without Thresholding in DMA and Slave Mode(p. 308) to
perform a data IN transfer.
7. Assertion of the USB_DIEPx_INT.XFERCOMPL interrupt indicates completion of the status IN phase
of the control transfer.
8. The previous step must be repeated until the USB_DIEPx_INT.XFERCOMPL interrupt is detected on
the endpoint, marking the completion of the control write transfer.
15.4.4.2.2.2 Control Read Transfers (SETUP, Data IN, Status OUT)
This section describes control read transfers.
Application Programming Sequence
1. Assertion of the USB_DOEPx_INT.SETUP Packet interrupt indicates that a valid SETUP packet
has been transferred to the application. See OUT Data Transfers in Slave and DMA Modes (p.
285) for more details. At the end of the Setup stage, the application must reprogram the
USB_DOEPx_TSIZ.SUPCNT field to 3 to receive the next SETUP packet.
2. If the last SETUP packet received before the assertion of the SETUP interrupt indicates a data IN
phase, program the core to perform a control IN transfer as explained in Generic Non-Periodic (Bulk
and Control) IN Data Transfers Without Thresholding in DMA and Slave Mode (p. 308) .
3. On a single IN data transfer on control endpoint 0, the application can transmit up to 64 bytes. To
transmit more than 64 bytes in the Data IN stage, the application must re-enable the endpoint to
transmit another 64 bytes, and must continue to do so, until it has transmitted all the data in the Data
stage.
4. The previous step must be repeated until the USB_DIEPx_INT.XFERCOMPL interrupt is detected
for every IN transfer on the endpoint.
5. The USB_DIEPx_INT.XFERCOMPL interrupt on the last IN data transfer marks the completion of the
control transfer’s Data stage.
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