EFM32WG Datasheet, PDF (240/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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The system part is accessed using USB registers from offset 0x000 to 0x018 and controls the voltage
regulator and enabling/disabling of the PHY and USB pins. This part is clocked by HFCORECLK_USB and
is accessed using an APB slave interface. The system part can thus be accessed independently of the
core part, without HFCORECLK_USBC running.
The core part is clocked by HFCORECLK_USBC and is accessed using an AHB slave interface. This
interface is used for accessing the FIFO contents and the registers in the core part starting at offset
0x3C000. An additional master interface is used by the internal DMA controller of the core. The core
part takes care of all the USB protocol related functionality. The clock to the system part must not be
disabled when the core part is active.
There are 8 pins associated with the USB. USB_VBUS should be connected to the VBUS (5V) pin on the
USB receptacle. It is connected to the voltage comparators and current sink/source in the PHY. USB_DP
and USB_DM are the USB D+ and D- pins. These are the USB data signaling pins. USB_ID is the OTG ID
pin used to detect the device type (A or B). This pin can be left unconnected when not used. USB_VREGI
is the input to the voltage regulator and USB_VREGO is the regulated output. USB_VBUSEN is used
to turn on and off VBUS power when operating as host-only or OTG A-Device. USB_DMPU is used to
enable/disable an external D- pull-up resistor. This is needed for low-speed device only. USB_VBUSEN
and USB_DMPU will be high-impedance until the pins are enabled from software. Thus, if a defined
level is required during start-up an external pull-up/pull-down can be used.
15.3.1 USB Initialization
The USB requires the device to run from a 48 MHz crystal (2500 ppm or better). The core part of
the USB will always run from HFCORECLK_USBC which is HFCLK undivided (48 MHz). The current
consumption for the rest of the device can be reduced by dividing down HFCORECLK using the
CMU_HFCORECLKDIV register. Bandwidth requirements for the specific USB application must be taken
into account when dividing down HFCORECLK.
Follow these steps to enable the USB:
1. Enable the clock to the system part by setting USB in CMU_HFCORECLKEN0.
2. If the internal USB regulator is bypassed (by applying 3.3V on USB_VREGI and USB_VREGO
externally), disable the regulator by setting VREGDIS in USB_CTRL.
3. If the PHY is powered from VBUS using the internal regulator, the VREGO sense circuit should be
enabled by setting VREGOSEN in USB_CTRL.
4. Enable the USB PHY pins by setting PHYPEN in USB_ROUTE.
5. If host or OTG dual-role device, set VBUSENAP in USB_CTRL to the desired value and then enable
the USB_VBUSEN pin in USB_ROUTE. Set the MODE for the pin to PUSHPULL.
6. If low-speed device, set DMPUAP in USB_CTRL to the desired value and then enable the
USB_DMPU pin in USB_ROUTE. Set the MODE for the pin to PUSHPULL.
7. Make sure HFXO is ready and selected. The core part requires the undivided HFCLK to be 48 MHz
when USB is active (during suspend/session-off a 32 kHz clock is used)..
8. Enable the clock to the core part by setting USBC in CMU_HFCORECLKEN0.
9. Wait for the core to come out of reset. This is easiest done by polling a core register with non-zero
reset value until it reads a non-zero value. This takes approximately 20 48-MHz cycles.
10.Start initializing the USB core as described in USB Core Description.
15.3.2 Configurations
The USB can be used as Device, OTG Dual Role Device or Host. The sections below describe the
different configurations. External ESD protection and series resistors for impedance matching are
required. The voltage regulator requires a 4.7 uF external decoupling capacitor on the input and a 1 uF
external decoupling capacitor on the output. Decoupling not related to USB is not shown in the figures.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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