EFM32WG Datasheet, PDF (516/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Bit
31:6
5
4
3:0
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
PULSEFILT
0
RW
Enable a one-cycle pulse filter for pulse extender
Pulse Filter
Value
0
1
Description
Filter is disabled. Pulses must be at least 2 cycles long for reliable detection.
Filter is enabled. Pulses must be at least 3 cycles long for reliable detection.
PULSEEN
0
RW
Pulse Generator/Extender Enable
Filter LEUART output through pulse generator and the LEUART input through the pulse extender.
PULSEW
0x0
RW
Pulse Width
Configure the pulse width of the pulse generator as a number of 32.768 kHz clock cycles.
19.5.17 LEUARTn_FREEZE - Freeze Register
Offset
0x040
Reset
Access
Bit Position
Name
Bit
31:1
0
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
REGFREEZE
0
RW
Register Update Freeze
When set, the update of the LEUART is postponed until this bit is cleared. Use this bit to update several registers simultaneously.
Value
0
1
Mode
UPDATE
FREEZE
Description
Each write access to a LEUART register is updated into the Low Frequency domain
as soon as possible.
The LEUART is not updated with the new written value.
19.5.18 LEUARTn_SYNCBUSY - Synchronization Busy Register
Offset
0x044
Reset
Access
Bit Position
Name
Bit
Name
Reset
Access Description
31:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
7
PULSECTRL
0
R
PULSECTRL Register Busy
Set when the value written to PULSECTRL is being synchronized.
6
TXDATA
0
R
TXDATA Register Busy
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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