EFM32WG Datasheet, PDF (471/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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17.4 Register Map
The offset register address is relative to the registers base address.
Offset
Name
Type
Description
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C
0x040
0x044
0x048
0x04C
0x050
0x054
0x058
0x05C
USARTn_CTRL
USARTn_FRAME
USARTn_TRIGCTRL
USARTn_CMD
USARTn_STATUS
USARTn_CLKDIV
USARTn_RXDATAX
USARTn_RXDATA
USARTn_RXDOUBLEX
USARTn_RXDOUBLE
USARTn_RXDATAXP
USARTn_RXDOUBLEXP
USARTn_TXDATAX
USARTn_TXDATA
USARTn_TXDOUBLEX
USARTn_TXDOUBLE
USARTn_IF
USARTn_IFS
USARTn_IFC
USARTn_IEN
USARTn_IRCTRL
USARTn_ROUTE
USARTn_INPUT
USARTn_I2SCTRL
RW
Control Register
RW
USART Frame Format Register
RW
USART Trigger Control register
W1
Command Register
R
USART Status Register
RW
Clock Control Register
R
RX Buffer Data Extended Register
R
RX Buffer Data Register
R
RX Buffer Double Data Extended Register
R
RX FIFO Double Data Register
R
RX Buffer Data Extended Peek Register
R
RX Buffer Double Data Extended Peek Register
W
TX Buffer Data Extended Register
W
TX Buffer Data Register
W
TX Buffer Double Data Extended Register
W
TX Buffer Double Data Register
R
Interrupt Flag Register
W1
Interrupt Flag Set Register
W1
Interrupt Flag Clear Register
RW
Interrupt Enable Register
RW
IrDA Control Register
RW
I/O Routing Register
RW
USART Input Register
RW
I2S Control Register
17.5 Register Description
17.5.1 USARTn_CTRL - Control Register
Offset
0x000
Reset
Access
Bit Position
Name
Bit
Name
Reset
Access Description
31
SMSDELAY
0
RW
Synchronous Master Sample Delay
Delay Synchronous Master sample point to the next setup edge to improve timing and allow communication at higher speeds.
30
MVDIS
0
RW
Majority Vote Disable
Disable majority vote for 16x, 8x and 6x oversampling modes.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
471
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