EFM32WG Datasheet, PDF (92/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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8.7.24 DMA_CTRL - DMA Control Register
Offset
0x1010
Reset
Access
Bit Position
Name
Bit
Name
Reset
Access Description
31:2
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
1
PRDU
0
RW
Prevent Rect Descriptor Update
Allows the reuse of a rect descriptor. When active CH0 and no others can have RDS set
0
DESCRECT
0
RW
Descriptor Specifies Rectangle
Word 4 in dma descriptor specifies WIDTH, HEIGHT and SRCSTRIDE for rectangle copies. WIDTH is given by bits 9:0, HEIGHT
is given by bits 19:10, and SRCSTRIDE is given by bits 30:20
8.7.25 DMA_RDS - DMA Retain Descriptor State
Offset
0x1014
Reset
Access
Bit Position
Name
Bit
31:12
11
10
9
8
7
6
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RDSCH11
0
RW
Retain Descriptor State
Speed up execution of consecutive DMA requests from the same channel by not reading descriptor at the start of every arbitration
cycle if the next channel is the same as the previous
RDSCH10
0
RW
Retain Descriptor State
Speed up execution of consecutive DMA requests from the same channel by not reading descriptor at the start of every arbitration
cycle if the next channel is the same as the previous
RDSCH9
0
RW
Retain Descriptor State
Speed up execution of consecutive DMA requests from the same channel by not reading descriptor at the start of every arbitration
cycle if the next channel is the same as the previous
RDSCH8
0
RW
Retain Descriptor State
Speed up execution of consecutive DMA requests from the same channel by not reading descriptor at the start of every arbitration
cycle if the next channel is the same as the previous
RDSCH7
0
RW
Retain Descriptor State
Speed up execution of consecutive DMA requests from the same channel by not reading descriptor at the start of every arbitration
cycle if the next channel is the same as the previous
RDSCH6
0
RW
Retain Descriptor State
Speed up execution of consecutive DMA requests from the same channel by not reading descriptor at the start of every arbitration
cycle if the next channel is the same as the previous
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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