EFM32WG Datasheet, PDF (216/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Bit
27:10
9:8
7:2
1:0
Name
Reset
Access Description
Enables or disables half cycle duration of the ALE strobe in the last address setup cycle.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
ADDRHOLD
0x3
RW
Address Hold Time
Sets the number of cycles the address is held after ALE is asserted.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
ADDRSETUP
0x3
RW
Address Setup Time
Sets the number of cycles the address is driven onto the ADDRDAT bus before ALE is asserted. If set to 0, 1 cycle is inserted by HW.
14.5.8 EBI_RDTIMING1 - Read Timing Register 1
Offset
0x01C
Reset
Access
Bit Position
Name
Bit
31
30
29
28
27:18
17:16
15:14
13:8
7:2
1:0
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
PAGEMODE
0
RW
Page Mode Access Enable
Enables or disables page mode reads.
PREFETCH
0
RW
Prefetch Enable
Enables or disables prefetching of data from sequential address.
HALFRE
0
RW
Half Cycle REn Strobe Duration Enable
Enables or disables half cycle duration of the REn strobe in the last RDSTRB cycle.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RDHOLD
0x3
RW
Read Hold Time
Sets the number of cycles CSn is held active after the REn is deasserted. This interval is used for bus turnaround.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RDSTRB
0x3F
RW
Read Strobe Time
Sets the number of cycles the REn is held active. After the specified number of cycles, data is read. If set to 0, 1 cycle is inserted by HW.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RDSETUP
0x3
RW
Read Setup Time
Sets the number of cycles the address setup before REn is asserted.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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