EFM32WG Datasheet, PDF (343/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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3. The core remains in Suspend mode.
4. The Resume signaling from the host is detected. A Resume Detected interrupt is generated.
5. The application clears the Gate hclk bit and the Stop PHY Clock bit.
6. The host finishes Resume signaling.
7. The core is in normal operating mode.
Device Mode Suspend and Remote Wakeup With Clock Gating
Sequence of operations:
1. The core detects a USB suspend and generates a Suspend Detected interrupt.
2. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register. The
application sets the Gate hclk bit in the Power and Clock Gating Control register, the core gates hclk.
3. The core remains in Suspend mode.
4. The application clears the Gate hclk bit and the Stop PHY Clock bit.
5. The application sets the Remote Wakeup bit in the Device Control register, the core starts driving
Remote Wakeup signaling.
6. The host drives Resume signaling.
7. The core is in normal operating mode.
Device Mode Session End and Start With Clock Gating
Sequence of operations:
1. The core detects a USB suspend, and generates a Suspend Detected interrupt. The host turns off
VBUS.
2. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register. The
application sets the Gate hclk bit in the Power and Clock Gating Control register, and the core gates
hclk.
3. The core remains in Low-Power mode.
4. The new session is detected (A session-valid voltage is detected). A New Session Detected interrupt
is generated.
5. The application clears the Gate hclk and Stop PHY Clock bits.
6. The core detects USB reset.
7. The core is in normal operating mode
Device Mode Session End and SRP With Clock Gating
Sequence of operations:
1. The core detects a USB suspend, and generates a Suspend Detected interrupt. The host turns off
VBUS.
2. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register. The
application sets the Gate hclk bit in the Power and Clock Gating Control register, and the core gates
hclk.
3. The core remains in Low-Power mode.
4. The application clears the Gate hclk and Stop PHY Clock bits.
5. The application sets the SRP Request bit, and the core drives data line and VBUS pulsing.
6. The host turns on VBUS, detects device connection, and drives a USB reset.
7. The core is in normal operating mode.
15.4.9 Register Usage
Only the Core Global, Power and Clock Gating, Data FIFO Access, and Host Port registers can be
accessed in both Host and Device modes. When the core is operating in one mode, either Device or
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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