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16.3.11 Using 10-bit Addresses
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When using 10-bit addresses in slave mode, set the I2Cn_SADDR register to 1111 0XX where XX
are the two most significant bits of the 10-bit address, and set I2Cn_SADDRMASK to 0xFF. Address
matches will now be given on all 10-bit addresses where the two most significant bits are correct.
When receiving an address match, the slave must acknowledge the address and receive the first data
byte. This byte contains the second part of the 10-bit address. If it matches the address of the slave,
the slave should ACK the byte to continue the transmission, and if it does not match, the slave should
NACK it.
When the master is operating as a master transmitter, the data bytes will follow after the second address
byte. When the master is operating as a master receiver however, a repeated START condition is sent
after the second address byte. The address sent after this repeated START is equal to the first of the
address bytes transmitted previously, but now with the R/W byte set, and only the slave that found a
match on the entire 10-bit address in the previous message should ACK this address. The repeated
start should take the master into a master receiver mode, and after the single address byte sent this
time around, the slave begins transmission to the master.
16.3.12 Error Handling
16.3.12.1 ABORT Command
Some bus errors may require software intervention to be resolved. The I²C module provides an ABORT
command, which can be set in I2Cn_CMD, to help resolve bus errors.
When the bus for some reason is locked up and the I²C module is in the middle of a transmission it
cannot get out of, or for some other reason the I²C wants to abort a transmission, the ABORT command
can be used.
Setting the ABORT command will make the I²C module discard any data currently being transmitted
or received, release the SDA and SCL lines and go to an idle mode. ABORT effectively makes the I²C
module forget about any ongoing transfers.
16.3.12.2 Bus Reset
A bus reset can be performed by setting the START and STOP commands in I2Cn_CMD while the
transmit buffer is empty. A START condition will then be transmitted, immediately followed by a STOP
condition. A bus reset can also be performed by transmitting a START command with the transmit buffer
empty and AUTOSE set.
16.3.12.3 I²C-Bus Errors
An I²C-bus error occurs when a START or STOP condition is misplaced, which happens when the value
on SDA changes while SCL is high during bit-transmission on the I²C-bus. If the I²C module is part of
the current transmission when a bus error occurs, any data currently being transmitted or received is
discarded, SDA and SCL are released, the BUSERR interrupt flag in I2Cn_IF is set to indicate the error,
and the module automatically takes a course of action as defined in Table 16.10 (p. 430) .
Table 16.10. I²C Bus Error Response
In a master/slave operation
Misplaced START
Treated as START. Receive address.
Misplaced STOP
Go idle. Perform any pending actions.
16.3.12.4 Bus Lockup
A lockup occurs when a master or slave on the I²C-bus has locked the SDA or SCL at a low value,
preventing other devices from putting high values on the bus, and thus making communication on the
bus impossible.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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