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entering EM0 again (due to USB resume/reset signaling or any other wake-up interrupt) the regulator
switches back to using the value specified in BIASPROGEM01 in USB_CTRL.
15.3.5 Interrupts and PRS
Interrupts from the core and system part share a common USB interrupt line to the CPU. The interrupt
flags for the system part are grouped together in the USB_IF register. The interrupt events from the core
are controlled by several core interrupt flag registers.
There are two PRS outputs from the USB: SOF and SOFSR. In Host mode, SOF toggles every time
an SOF is generated. In Device mode, SOF toggles every time an SOF token is received from the USB
host or when an SOF token is missed at the start of frame. In Host mode, SOFSR toggles every time
an SOF is successfully transmitted. In Device mode, SOFSR toggles only when a valid SOF token is
received from the USB host. Both PRS outputs must be synchronized in the PRS when used (i.e. it is an
asynchronous PRS output). The edge-to-pulse converter in the PRS can be used to convert the edges
into pulses if needed. The PRS outputs go to 0 in EM2/3.
15.3.6 USB in EM2
During suspend and session-off EM2 should be used to save power and meet the average current
requirements dictated by the USB standard. Before entering EM2, HFCORECLK_USBC must be switched
from 48 MHz to 32 kHz (LFXO or LFRCO). This is done using the CMU_CMD and CMU_STATUS
registers. While HFCORECLK_USBC is 32 kHz, the USB core registers (starting from offset 0x3C000)
cannot be accessed and the the internal DMA in the USB core will not be able to access the AHB bus.
Upon EM2 wake-up, HFCORECLK_USBC must be switched back to 48 MHz before accessing the core
registers. The device always starts up from HFRCO so software must restart HFXO and switch from
HFRCO to HFXO. The USB system clock, HFCORECLK_USB, must be kept enabled during EM2. The
USB system registers can be accessed immediately upon EM2 wake-up, while running from HFRCO.
Follow the steps outlined the USB Core Description when entering EM2 during suspend and session-off.
The FIFO content is lost when entering EM2. In addition, most of the USB core registers are reset and
therefore need to be backed up in RAM.
EM3 cannot be used when the USB is active. However, EM3 can be used while waiting for the internal
voltage regulator to be activated (i.e. VBUS becomes 5V).
15.4 USB Core Description
This section describes the programming requirements for the USB Core in Host and Device modes.
Important features/parameters for the core are:
• HNP- and SRP-Capable OTG (Device and Host)
• Internal DMA (Buffer Pointer Based)
• Dedicated TX FIFOS for each endpoint in device mode
• 6 IN/OUT endpoints in addition to endpoint 0 (in device mode)
• 14 host channels (in host mode)
• Dynamic FIFO sizing
• Non-Periodic Request Queue Depth: 8
• Host Mode Periodic Request Queue Depth: 8
The core has the following limitations:
• Link Power Management (LPM) is not supported
• ADP is not supported
Portions Copyright © 2010 Synopsys, Inc. Used with permission. Synopsys and DesignWare are
registered trademarks of Synopsys, Inc.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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