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Figure 14.46. EBI TFT Interrupts
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VSYNC, HSYNC
HSYNC
HS.Y..NC _...
HBPORCH
... ...
HSYNC
VFPORCH, HSYNC
HSYNC
HSYNC
... ...
... ...
HSYNC
HSZ+ 1
Visible Display
VBPORCH
HFPORCH
The DDEMPTY interrupt flag indicates that the EBI_TFTDD register is empty during Direct Drive from
internal memory. The DDJIT interrupt flag indicates that the DCLKPERIOD is not met during Direct Drive
operation.
Setting one of the interrupt flags will result in an EBI interrupt if the corresponding interrupt enable bit is
set in the EBI_IEN register. All generated interrupts from the EBI will activate the same interrupt vector
when enabled.
14.3.22 DMA Request
In internal Direct Drive mode, when the DD bitfield in EBI_TFTCTRL register is INTERNAL, the TFT
controller sends out a DMA request when the pixel buffer EBI_TFTDD is empty and needs to be filled.
This request is initially set and it is cleared when EBI_TFTDD is written. It is set again once the pixel
data has been transferred to the display. One DMA request is generated for each visible pixel.
The masking and alpha blending hardware uses three DMA requests related to the status of thee internal
masking and alpha blending registers EBI_TFTPIXEL0, EBI_TFTPIXEL1, and EBI_TFTPIXEL. The
DMA request for EBI_TFTPIXEL0 indicates that new data can be written to be used for internal masking
or alpha blending. This request is initially set and it is cleared when EBI_TFTPIXEL0 is written. The
request is set again when EBI_TFTPIXEL is read. The DMA request for EBI_TFTPIXEL1 is initially set
and it is cleared when EBI_TFTPIXEL1 is written. Only when both EBI_TFTPIXEL0 and EBI_TFTPIXEL1
have been written, will a EBI_TFTPIXEL read set the DMA request for EBI_TFTPIXEL1 again. The DMA
request for EBI_TFTPIXEL indicates whether new masked and/or blended data is available for reading
in EBI_TFTPIXEL or not. It is set after completion of internal masking and alpha blending in reaction to
a write to EBI_TFTPIXEL0. It is cleared when EBI_TFTPIXEL is read.
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