EFM32WG Datasheet, PDF (134/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

11.4 Register Map
...the world's most energy friendly microcontrollers
The offset register address is relative to the registers base address.
Offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C
0x040
0x044
0x050
0x054
0x058
0x060
0x068
0x070
0x078
0x07C
0x080
0x084
Name
CMU_CTRL
CMU_HFCORECLKDIV
CMU_HFPERCLKDIV
CMU_HFRCOCTRL
CMU_LFRCOCTRL
CMU_AUXHFRCOCTRL
CMU_CALCTRL
CMU_CALCNT
CMU_OSCENCMD
CMU_CMD
CMU_LFCLKSEL
CMU_STATUS
CMU_IF
CMU_IFS
CMU_IFC
CMU_IEN
CMU_HFCORECLKEN0
CMU_HFPERCLKEN0
CMU_SYNCBUSY
CMU_FREEZE
CMU_LFACLKEN0
CMU_LFBCLKEN0
CMU_LFAPRESC0
CMU_LFBPRESC0
CMU_PCNTCTRL
CMU_LCDCTRL
CMU_ROUTE
CMU_LOCK
Type
RW
RW
RW
RW
RW
RW
RW
RWH
W1
W1
RW
R
R
W1
W1
RW
RW
RW
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
Description
CMU Control Register
High Frequency Core Clock Division Register
High Frequency Peripheral Clock Division Register
HFRCO Control Register
LFRCO Control Register
AUXHFRCO Control Register
Calibration Control Register
Calibration Counter Register
Oscillator Enable/Disable Command Register
Command Register
Low Frequency Clock Select Register
Status Register
Interrupt Flag Register
Interrupt Flag Set Register
Interrupt Flag Clear Register
Interrupt Enable Register
High Frequency Core Clock Enable Register 0
High Frequency Peripheral Clock Enable Register 0
Synchronization Busy Register
Freeze Register
Low Frequency A Clock Enable Register 0 (Async Reg)
Low Frequency B Clock Enable Register 0 (Async Reg)
Low Frequency A Prescaler Register 0 (Async Reg)
Low Frequency B Prescaler Register 0 (Async Reg)
PCNT Control Register
LCD Control Register
I/O Routing Register
Configuration Lock Register
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
134
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