EFM32WG Datasheet, PDF (372/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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15.6.31 USB_HPTXSTS - Host Periodic Transmit FIFO/Queue Status
Register
This read-only register contains the free space information for the Periodic TxFIFO and the Periodic
Transmit Request Queue.
Offset
0x3C410
Bit Position
Reset
Access
Name
Bit
31:24
23:16
15:0
Name
Reset
Access Description
PTXQTOP
0x00
R
Top of the Periodic Transmit Request Queue
This indicates the Entry in the Periodic Tx Request Queue that is currently being processes by the MAC. This register is used for
debugging.
Bit [7]: Odd/Even Frame. 0: send in even Frame, 1: send in odd Frame.
Bits [6:3]: Channel/endpoint number.
Bits [2:1]: Type. 00: IN/OUT, 01: Zero-length packet, 10: Unused, 11: Disable channel command.
Bit [0]: Terminate (last Entry for the selected channel/endpoint).
PTXQSPCAVAIL
0x08
R
Periodic Transmit Request Queue Space Available
Indicates the number of free locations available to be written in the Periodic Transmit Request Queue. This queue holds both IN
and OUT requests.
PTXFSPCAVAIL
0x0200
R
Periodic Transmit Data FIFO Space Available
Indicates the number of free locations available to be written to in the Periodic TxFIFO. Values are in terms of 32-bit words.
15.6.32 USB_HAINT - Host All Channels Interrupt Register
When a significant event occurs on a channel, the Host All Channels Interrupt register interrupts the
application using the Host Channels Interrupt bit of the Core Interrupt register (USB_GINTSTS.HCHINT).
There is one interrupt bit per channel. Bits in this register are set and cleared when the application sets
and clears bits in the corresponding Host Channel x Interrupt register.
Offset
0x3C414
Bit Position
Reset
Access
Name
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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