EFM32WG Datasheet, PDF (88/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

...the world's most energy friendly microcontrollers
Bit
Name
Reset
Access Description
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service
the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.
5
CH5SREQSTATUS
0
R
Channel 5 Single Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service
the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.
4
CH4SREQSTATUS
0
R
Channel 4 Single Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service
the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.
3
CH3SREQSTATUS
0
R
Channel 3 Single Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service
the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.
2
CH2SREQSTATUS
0
R
Channel 2 Single Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service
the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.
1
CH1SREQSTATUS
0
R
Channel 1 Single Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service
the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.
0
CH0SREQSTATUS
0
R
Channel 0 Single Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service
the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.
8.7.20 DMA_IF - Interrupt Flag Register
Offset
0x1000
Reset
Access
Bit Position
Name
Bit
31
30:12
11
10
9
8
7
6
5
Name
Reset
Access Description
ERR
0
R
DMA Error Interrupt Flag
This flag is set when an error has occurred on the AHB bus.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
CH11DONE
0
R
DMA Channel 11 Complete Interrupt Flag
Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for the channel.
CH10DONE
0
R
DMA Channel 10 Complete Interrupt Flag
Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for the channel.
CH9DONE
0
R
DMA Channel 9 Complete Interrupt Flag
Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for the channel.
CH8DONE
0
R
DMA Channel 8 Complete Interrupt Flag
Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for the channel.
CH7DONE
0
R
DMA Channel 7 Complete Interrupt Flag
Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for the channel.
CH6DONE
0
R
DMA Channel 6 Complete Interrupt Flag
Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for the channel.
CH5DONE
0
R
DMA Channel 5 Complete Interrupt Flag
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
88
www.energymicro.com