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EFM32WG Datasheet, PDF (382/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.
...the world's most energy friendly microcontrollers
status in the USB_DIEP0INT/USB_DIEPx_INT register can be masked by writing to the corresponding
bit in this register. Status bits are masked by default.
Offset
0x3C810
Reset
Access
Bit Position
Name
Bit
31:14
13
12:9
8
7
6
5
4
3
2
1
0
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
NAKMSK
0
RW
NAK interrupt Mask
Set to 1 to unmask NAK Interrupt.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
TXFIFOUNDRNMSK
0
RW
Fifo Underrun Mask
Set to 1 to unmask TXFIFOUNDRN Interrupt.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
INEPNAKEFFMSK
0
RW
IN Endpoint NAK Effective Mask
Set to 1 to unmask INEPNAKEFF Interrupt.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
INTKNTXFEMPMSK
0
RW
IN Token Received When TxFIFO Empty Mask
Set to 1 to unmask INTKNTXFEMP Interrupt.
TIMEOUTMSK
0
RW
Timeout Condition Mask
Set to 1 to unmask Interrupt TIMEOUT. Applies to Non-isochronous endpoints.
AHBERRMSK
0
RW
AHB Error Mask
Set to 1 to unmask AHBERR Interrupt.
EPDISBLDMSK
0
RW
Set to 1 to unmask EPDISBLD Interrupt.
Endpoint Disabled Interrupt Mask
XFERCOMPLMSK
0
RW
Transfer Completed Interrupt Mask
Set to 1 to unmask XFERCOMPL Interrupt.
15.6.44 USB_DOEPMSK - Device OUT Endpoint Common Interrupt Mask
Register
This register works with each of the Device OUT Endpoint Interrupt (USB_DOEP0INT/
USB_DOEPx_INT) registers for all endpoints to generate an interrupt per OUT endpoint. The OUT
endpoint interrupt for a specific status in the USB_DOEP0INT/USB_DOEPx_INT register can be masked
by writing into the corresponding bit in this register. Status bits are masked by default.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
382
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