EFM32WG Datasheet, PDF (608/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Bit
Name
Reset
Access Description
Value
0
1
2
3
Mode
BOTH
UP
DOWN
NONE
Description
Counts up on up-count and down on down-count events.
Only counts up on up-count events.
Only counts down on down-count events.
Never counts.
9
S1CDIR
0
RW
Count direction determined by S1
S1 gives the direction of counting when in the OVSSINGLE or EXTCLKSINGLE modes. When S1 is high, the count direction is given
by CNTDIR, and when S1 is low, the count direction is the opposite
8
HYST
0
RW
Enable Hysteresis
When hysteresis is enabled, the PCNT will always overflow and underflow to TOP/2.
7:6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
5
RSTEN
0
RW
Enable PCNT Clock Domain Reset
The PCNT clock domain is asynchronously held in reset when this bit is set. The reset is synchronously released two PCNT clock
edges after this bit is cleared. If external clock used the reset should be performed by setting and clearing the bit without pending
for SYNCBUSY bit.
4
FILT
0
RW
Enable Digital Pulse Width Filter
The filter passes all high and low periods that are at least 5 clock cycles long. This filter is only available in OVSSINGLE mode.
3
EDGE
0
RW
Edge Select
Determines the polarity of the incoming edges. This bit should be written when PCNT is in DISABLE mode, otherwise the behavior
is unpredictable. This bit is ignored in EXTCLKSINGLE mode.
Value
0
1
Mode
POS
NEG
Description
Positive edges on the PCNTn_S0IN inputs are counted in OVSSINGLE mode.
Negative edges on the PCNTn_S0IN inputs are counted in OVSSINGLE mode, and
the counter direction is inverted in EXTCLKQUAD mode.
2
CNTDIR
0
RW
Non-Quadrature Mode Counter Direction Control
The direction of the counter must be set in the OVSSINGLE and EXTCLKSINGLE modes. This bit is ignored in EXTCLKQUAD mode
as the direction is automatically detected.
Value
0
1
Mode
UP
DOWN
Description
Up counter mode.
Down counter mode.
1:0
MODE
0x0
RW
Mode Select
Selects the mode of operation. The corresponding clock source must be selected from the CMU.
Value
0
1
2
3
Mode
DISABLE
OVSSINGLE
EXTCLKSINGLE
EXTCLKQUAD
Description
The module is disabled.
Single input LFACLK oversampling mode (available in EM0-EM2).
Externally clocked single input counter mode (available in EM0-EM3).
Externally clocked quadrature decoder mode (available in EM0-EM3).
24.5.2 PCNTn_CMD - Command Register (Async Reg)
For more information about Asynchronous Registers please see Section 5.3 (p. 21) .
Offset
0x004
Reset
Access
Bit Position
Name
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
608
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