EFM32WG Datasheet, PDF (830/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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List of Tables
2.1. Register Access Types ............................................................................................................................ 3
3.1. Energy Mode Description ......................................................................................................................... 8
3.2. EFM32WG Microcontroller Series .............................................................................................................. 8
4.1. Interrupt Request Lines (IRQ) .................................................................................................................. 13
5.1. Memory System Core Peripherals ............................................................................................................ 18
5.2. Memory System Low Energy Peripherals ................................................................................................... 19
5.3. Memory System Peripherals .................................................................................................................... 20
5.4. Device Information Page Contents ........................................................................................................... 24
7.1. MSC Flash Memory Mapping .................................................................................................................. 33
7.2. Lock Bits Page Structure ........................................................................................................................ 33
7.3. Revision Number Interpretation ................................................................................................................ 34
8.1. AHB bus transfer arbitration interval ......................................................................................................... 52
8.2. DMA channel priority ............................................................................................................................. 52
8.3. DMA cycle types ................................................................................................................................... 54
8.4. channel_cfg for a primary data structure, in memory scatter-gather mode ......................................................... 58
8.5. channel_cfg for a primary data structure, in peripheral scatter-gather mode ...................................................... 60
8.6. Address bit settings for the channel control data structure ............................................................................. 63
8.7. src_data_end_ptr bit assignments ............................................................................................................ 64
8.8. dst_data_end_ptr bit assignments ............................................................................................................ 65
8.9. channel_cfg bit assignments ................................................................................................................... 65
8.10. DMA cycle of six words using a word increment ........................................................................................ 68
8.11. DMA cycle of 12 bytes using a halfword increment .................................................................................... 68
8.12. User data assignments when DESCRECT is set ....................................................................................... 70
9.1. RMU Reset Cause Register Interpretation ................................................................................................ 100
10.1. EMU Energy Mode Overview ............................................................................................................... 108
10.2. EMU Entering a Low Energy Mode ....................................................................................................... 110
10.3. EMU Wakeup Triggers from Low Energy Modes ...................................................................................... 111
11.1. Configuration For Operating Frequencies ............................................................................................... 133
13.1. Reflex Producers ............................................................................................................................... 164
13.2. Reflex Consumers ............................................................................................................................. 165
14.1. EBI Intrapage hit condition for read on address Addr (non-mentioned Addr bits are unchanged) ......................... 179
14.2. EBI Enabling EBI_ADDR lines for transaction with address Addr and data Data ............................................. 182
14.3. EBI Mapping of AHB Transactions to External Device Transactions ............................................................. 185
14.4. EBI NAND Flash Register Select .......................................................................................................... 189
14.5. EBI NAND Flash Write Timing ............................................................................................................. 191
14.6. EBI NAND Flash Read Timing ............................................................................................................. 192
14.7. EBI NAND Flash Read/Write Timing Requirements .................................................................................. 192
14.8. EBI ECC Bit/Column Parity .................................................................................................................. 194
14.9. EBI ECC Byte/Row Parity ................................................................................................................... 194
14.10. EBI EBI_ECCPARITY valid bits .......................................................................................................... 195
14.11. EBI Error Detection Result ................................................................................................................. 195
15.1. Host Programming Operations ............................................................................................................. 255
15.2. ...................................................................................................................................................... 284
15.3. ...................................................................................................................................................... 328
15.4. ...................................................................................................................................................... 329
16.1. I²C Reserved I²C Addresses ................................................................................................................ 414
16.2. I²C Clock Mode Examples ................................................................................................................... 416
16.3. I²C Interactions in Prioritized Order ....................................................................................................... 420
16.4. I²C Master Transmitter ........................................................................................................................ 422
16.5. I²C Master Receiver ........................................................................................................................... 423
16.6. I²C STATE Values ............................................................................................................................. 425
16.7. I²C Transmission Status ...................................................................................................................... 425
16.8. I²C Slave Transmitter ......................................................................................................................... 428
16.9. I²C - Slave Receiver .......................................................................................................................... 429
16.10. I²C Bus Error Response .................................................................................................................... 430
17.1. USART Asynchronous vs. Synchronous Mode ........................................................................................ 447
17.2. USART Pin Usage ............................................................................................................................. 447
17.3. USART Data Bits ............................................................................................................................... 448
17.4. USART Stop Bits ............................................................................................................................... 448
17.5. USART Parity Bits ............................................................................................................................. 449
17.6. USART Oversampling ......................................................................................................................... 449
17.7. USART Baud Rates @ 4MHz Peripheral Clock ....................................................................................... 450
17.8. USART SPI Modes ............................................................................................................................ 462
17.9. USART I2S Modes ............................................................................................................................ 466
17.10. USART IrDA Pulse Widths ................................................................................................................. 470
18.1. UART Limitations ............................................................................................................................... 492
19.1. LEUART Parity Bit ............................................................................................................................. 495
19.2. LEUART Baud Rates ......................................................................................................................... 496
20.1. TIMER Counter Response in X2 Decoding Mode ..................................................................................... 525
20.2. TIMER Counter Response in X4 Decoding Mode ..................................................................................... 525
20.3. TIMER Events ................................................................................................................................... 536
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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