EFM32WG Datasheet, PDF (199/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Figure 14.35. EBI TFT Direct Drive from External Memory (non-multiplexed address/data)
EBI_A
Cont rol
ADDR
EBI
( EFM3 2 )
EBI_AD
DATA
EBI_DCLK
DATA
EBI_DATAEN
EBI_VSYNC, EBI_HSYNC
EBI_TFTCSn
Ext ernal
Mem ory
Device
TFT
Figure 14.36. EBI TFT Direct Drive from External Memory (multiplexed address/data)
EBI_ALE
Cont rol
EBI
( EFM3 2 )
Lat ch ^ADDR
EBI_AD
DATA
DATA
EBI_DCLK
EBI_DATAEN
EBI_VSYNC, EBI_HSYNC
EBI_TFTCSn
Ext ernal
Mem ory
Device
TFT
The start address for the frame transfer is defined in the EBI_TFTFRAMEBASE register. The Direct
Drive address is automatically incremented for each visible pixel and it does therefore not depend
on the programmed porch sizes. The address increment depends on the WIDTH bitfield in the
EBI_TFTCTRL register. The increment per visible pixel is 1 if the WIDTH bitfield in the EBI_TFTCTRL
register is programmed to BYTE and it is 2 if WIDTH is programmed to HALFWORD. Additionally a
horizontal stride is added to the Direct Drive address at the end of each visible line. This stride can
be programmed in the HSTRIDE bitfield of the EBI_TFTSTRIDE register. The first visible pixel always
corresponds to the address defined in the EBI_TFTFRAMEBASE register. On either the vertical or
horizontal synchronization event, as defined in the FBCTRIG bitfield of the EBI_TFTCTRL register,
the EBI_TFTFRAMEBASE register is copied into an internal frame base buffer (FBC). This allows
software to reprogram the EBI_TFTFRAMEBASE register based on VSYNC or HSYNC interrupts, which
in turn can be used to for example implement double buffering or scrolling schemes. The HSYNC
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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