EFM32WG Datasheet, PDF (374/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

...the world's most energy friendly microcontrollers
Bit
16:13
12
11:10
9
8
7
6
5
4
3
2
1
Name
Reset
Access Description
Value
0
1
2
Mode
HS
FS
LS
Description
High speed.
Full speed.
Low speed.
PRTTSTCTL
0x0
RW
Port Test Control
The application writes a nonzero value to this field to put the port into a Test mode, and the corresponding pattern is signaled on
the port.
Value
0
1
2
3
4
5
Mode
DISABLE
J
K
SE0NAK
PACKET
FORCE
Description
Test mode disabled.
Test_J mode.
Test_K mode.
Test_SE0_NAK mode.
Test_Packet mode.
Test_Force_Enable.
PRTPWR
0
RW
Port Power
The application uses this field to control power to this port. The core can clear this bit on an over current condition.
Value
0
1
Mode
OFF
ON
Description
Power off.
Power on.
PRTLNSTS
0x0
R
Port Line Status
Indicates the current logic level USB data lines. Bit [0]: Logic level of D+. Bit [1]: Logic level of D-.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
PRTRST
0
RW
Port Reset
When the application sets this bit, a reset sequence is started on this port. The application must time the reset period and clear this
bit after the reset sequence is complete. The application must leave this bit set for at least 10 ms to start a reset on the port. The
application can leave it set for another 10 ms in addition to the required minimum duration, before clearing the bit, even though there
is no maximum limit set by the USB standard.
PRTSUSP
0
RW1
Port Suspend
The application sets this bit to put this port in Suspend mode. The core only stops sending SOFs when this is set. To stop the PHY
clock, the application must set USB_PCGCCTL.STOPPCLK, which puts the PHY into suspend mode. The read value of this bit
reflects the current suspend status of the port. This bit is cleared by the core after a remote wakeup signal is detected or the application
sets the Port Reset bit or Port Resume bit in this register or the Resume/Remote Wakeup Detected Interrupt bit or Disconnect
Detected Interrupt bit in the Core Interrupt register (USB_GINTSTS.WKUPINT or USB_GINTSTS.DISCONNINT respectively). This
bit is cleared by the core even if there is no device connected to the Host.
PRTRES
0
RW
Port Resume
The application sets this bit to drive resume signaling on the port. The core continues to drive the resume signal until the application
clears this bit. If the core detects a USB remote wakeup sequence, as indicated by the Port Resume/Remote Wakeup Detected
Interrupt bit of the Core Interrupt register (USB_GINTSTS.WKUPINT), the core starts driving resume signaling without application
intervention and clears this bit when it detects a disconnect condition. The read value of this bit indicates whether the core is currently
driving resume signaling.
PRTOVRCURRCHNG
0
RW1
Port Overcurrent Change
The core sets this bit when the status of the Port Overcurrent Active bit (bit 4) in this register changes. This bit can be set only by
the core and the application should write 1 to clear it.
PRTOVRCURRACT
0
R
Port Overcurrent Active
Indicates the overcurrent condition of the port. When there is an overcurrent condition this bit is 1.
PRTENCHNG
0
RW1
Port Enable/Disable Change
The core sets this bit when the status of the Port Enable bit[2] of this register changes. This bit can be set only by the core and the
application should write 1 to clear it.
PRTENA
0
RW1
Port Enable
A port is enabled only by the core after a reset sequence, and is disabled by an overcurrent condition, a disconnect condition, or by
the application clearing this bit. The application cannot set this bit by a register write. It can only clear it to disable the port by writing
1. This bit does not trigger any interrupt to the application.
PRTCONNDET
0
RW1
Port Connect Detected
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
374
www.energymicro.com