EFM32WG Datasheet, PDF (102/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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9.4 Register Map
The offset register address is relative to the registers base address.
Offset
0x000
0x004
0x008
Name
RMU_CTRL
RMU_RSTCAUSE
RMU_CMD
Type
RW
R
W1
Description
Control Register
Reset Cause Register
Command Register
9.5 Register Description
9.5.1 RMU_CTRL - Control Register
Offset
0x000
Reset
Access
Bit Position
Name
Bit
Name
Reset
Access Description
31:2
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
1
BURSTEN
1
RW
Backup domain reset enable
This bit has to be cleared before accessing the registers in the BURTC.
0
LOCKUPRDIS
0
RW
Lockup Reset Disable
Set this bit to disable the LOCKUP signal (from the Cortex) from resetting the device.
9.5.2 RMU_RSTCAUSE - Reset Cause Register
Offset
0x004
Reset
Access
Bit Position
Name
Bit
31:16
15
14
13
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
BUMODERST
0
R
Backup mode reset
Set if the system has been in Backup mode. Must be cleared by software. Please see Section 10.3.4 (p. 111) for details on how
to interpret this bit.
BUBODREG
0
R
Backup Brown Out Detector Regulated Domain
Set if the Backup BOD sensing on regulated power triggers. Must be cleared by software. Please see Section 10.3.4.2 (p. 112)
for details on how to interpret this bit.
BUBODUNREG
0
R
Backup Brown Out Detector Unregulated Domain
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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