EFM32WG Datasheet, PDF (826/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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14.33. EBI TFT Size .................................................................................................................................. 197
14.34. EBI TFT Direct Drive from Internal Memory ........................................................................................... 198
14.35. EBI TFT Direct Drive from External Memory (non-multiplexed address/data) ................................................ 199
14.36. EBI TFT Direct Drive from External Memory (multiplexed address/data) ...................................................... 199
14.37. EBI Direct Drive Address ................................................................................................................... 200
14.38. EBI TFT Alpha Blending and Masking .................................................................................................. 201
14.39. EBI TFT Pixel Timing ........................................................................................................................ 204
14.40. EBI TFT Direct Drive Internal Timing ................................................................................................... 204
14.41. EBI TFT Direct Drive External Timing .................................................................................................. 204
14.42. EBI TFT Horizontal Porch Timing ........................................................................................................ 205
14.43. EBI TFT Vertical Porch Timing ........................................................................................................... 205
14.44. EBI TFT Pixel Timing: EBI_DCLK driven off Positive Edge Internal Clock .................................................... 205
14.45. EBI TFT Pixel Timing: EBI_DCLK driven off Negative Edge Internal Clock ................................................... 205
14.46. EBI TFT Interrupts ........................................................................................................................... 207
15.1. USB Block Diagram ........................................................................................................................... 239
15.2. Bus-powered Device .......................................................................................................................... 241
15.3. Self-powered Device .......................................................................................................................... 241
15.4. Self-powered Device (with bus-power switch) .......................................................................................... 242
15.5. OTG Dual Role Device (5V) ................................................................................................................ 243
15.6. OTG Dual Role Device (5V step-up regulator) ......................................................................................... 243
15.7. Host ................................................................................................................................................ 244
15.8. Transmit Transaction-Level Operation in Slave Mode ................................................................................ 251
15.9. Receive Transaction-Level Operation in Slave Mode ................................................................................ 251
15.10. Transmit FIFO Write Task in Slave Mode ............................................................................................. 256
15.11. Receive FIFO Read Task in Slave Mode .............................................................................................. 256
15.12. Normal Bulk/Control OUT/SETUP and Bulk/Control IN Transactions in Slave Mode ....................................... 258
15.13. Normal Bulk/Control OUT/SETUP and Bulk/Control IN Transactions in DMA Mode ........................................ 263
15.14. Interrupt Service Routine for Bulk/Control OUT Transaction in DMA Mode ................................................... 264
15.15. Normal Interrupt OUT/IN Transactions in Slave Mode ............................................................................. 268
15.16. Normal Interrupt OUT/IN Transactions in DMA Mode .............................................................................. 272
15.17. Normal Isochronous OUT/IN Transactions in Slave Mode ........................................................................ 276
15.18. Normal Isochronous OUT/IN Transactions in DMA Mode ......................................................................... 279
15.19. Processing a SETUP Packet .............................................................................................................. 287
15.20. Two-Stage Control Transfer ............................................................................................................... 290
15.21. Receive FIFO Packet Read in Slave Mode ........................................................................................... 291
15.22. Slave Mode Bulk OUT Transaction ...................................................................................................... 295
15.23. ISOC OUT Application Flow for Periodic Transfer Interrupt Feature ............................................................ 300
15.24. Isochronous OUT Core Internal Flow for Periodic Transfer Interrupt Feature ................................................ 301
15.25. Bulk IN Stall .................................................................................................................................... 305
15.26. USBTRDTIM Max Timing Case ERROR wrong image ............................................................................. 308
15.27. Slave Mode Bulk IN Transaction ......................................................................................................... 310
15.28. Slave Mode Bulk IN Transfer (Pipelined Transaction) .............................................................................. 312
15.29. Slave Mode Bulk IN Two-Endpoint Transfer .......................................................................................... 313
15.30. Periodic IN Application Flow for Periodic Transfer Interrupt Feature ............................................................ 317
15.31. Periodic IN Core Internal Flow for Periodic Transfer Interrupt Feature ......................................................... 319
15.32. SRP Detection by Core When Operating as A-device .............................................................................. 323
15.33. SRP Initiation by the Core When Acting as a B-Device ............................................................................ 324
15.34. HNP When the Core is an A-Device .................................................................................................... 325
15.35. HNP When the Core is a B-Device ..................................................................................................... 326
15.36. Core Interrupt Handler ...................................................................................................................... 334
16.1. I²C Overview .................................................................................................................................... 412
16.2. I²C-Bus Example ............................................................................................................................... 412
16.3. I²C START and STOP Conditions ......................................................................................................... 413
16.4. I²C Bit Transfer on I²C-Bus ................................................................................................................. 413
16.5. I²C Single Byte Write to Slave ............................................................................................................. 414
16.6. I²C Double Byte Read from Slave ......................................................................................................... 414
16.7. I²C Single Byte Write, then Repeated Start and Single Byte Read ............................................................... 414
16.8. I²C Master Transmitter/Slave Receiver with 10-bit Address ........................................................................ 415
16.9. I²C Master Receiver/Slave Transmitter with 10-bit Address ........................................................................ 415
16.10. I²C Master State Machine .................................................................................................................. 419
16.11. I²C Slave State Machine ................................................................................................................... 426
17.1. USART Overview ............................................................................................................................... 446
17.2. USART Asynchronous Frame Format .................................................................................................... 447
17.3. USART Transmit Buffer Operation ........................................................................................................ 451
17.4. USART Receive Buffer Operation ......................................................................................................... 453
17.5. USART Sampling of Start and Data Bits ................................................................................................ 454
17.6. USART Sampling of Stop Bits when Number of Stop Bits are 1 or More ....................................................... 454
17.7. USART Local Loopback ...................................................................................................................... 455
17.8. USART Half Duplex Communication with External Driver ........................................................................... 456
17.9. USART Transmission of Large Frames .................................................................................................. 457
17.10. USART Transmission of Large Frames, MSBF ...................................................................................... 458
17.11. USART Reception of Large Frames ..................................................................................................... 458
17.12. USART ISO 7816 Data Frame Without Error ......................................................................................... 460
17.13. USART ISO 7816 Data Frame With Error ............................................................................................. 460
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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