EFM32WG Datasheet, PDF (231/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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14.5.31 EBI_TFTTIMING - TFT Timing Register
Offset
0x078
Bit Position
Reset
Access
Name
Bit
31:30
29:28
27:26
25:24
23
22:12
11
10:0
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
TFTHOLD
0x0
RW
TFT Hold Time
Sets the number of internal clock cycles the RGB data is held after the active edge of EBI_DCLK.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
TFTSETUP
0x0
RW
TFT Setup Time
Sets the number of internal clock cycles the RGB data is driven before the active edge of EBI_DCLK.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
TFTSTART
0x000
RW
TFT Direct Drive Transaction Start
Sets the starting position of the External Direct Drive Transaction relative to the DCLK inactive edge.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
DCLKPERIOD
0x000
RW
TFT Direct Drive Transaction (EBI_DCLK) Period
Sets the Direct Drive transaction (EBI_DCLK) period in internal cycles. Set to required cycle count minus 1.
14.5.32 EBI_TFTPOLARITY - TFT Polarity Register
Offset
0x07C
Reset
Access
Bit Position
Name
Bit
31:5
4
3
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
VSYNCPOL
0
RW
Sets the polarity of the EBI_VSYNC line.
VSYNC Polarity
Value
0
1
Mode
ACTIVELOW
ACTIVEHIGH
Description
VSYNC is active low.
VSYNC is active high.
HSYNCPOL
0
RW
Sets the polarity of the EBI_HSYNC line.
Address Latch Polarity
Value
0
Mode
ACTIVELOW
Description
HSYNC is active low.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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