EFM32WG Datasheet, PDF (205/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Figure 14.42. EBI TFT Horizontal Porch Timing
HBPORCH
(0, 1, 2, ...)
EBI_DCLK
...
...
EBI_AD[ 15:0]
HORIZONTAL BAC..K. PORCH
P0
EBI_DATAEN
...
EBI_HSYNC
HSYNCSTART
(0, 1, 2, ...)
...
HSYNC
(1, 2, 3, ...)
HSZ
(1, 2, 3, ...)
P1
HFPORCH
(0, 1, 2, ...)
...
...
...
...
...
PHSZ
HORIZONTAL FRON...T PORCH
...
...
The timing parameters related to the vertical timing are shown in Figure 14.43 (p. 205) . These
parameters are defined as line or EBI_HSYNC counts. The vertical porch widths are defined in the
VBPORCH and VFPORCH bitfields of the EBI_TFTVPORCH register. A porch which has its width
parameter programmed to 0 will be skipped. The width of the vertical synchronization pulse EBI_VSYNC
is programmed via the VSYNC bitfield in the EBI_TFTVPORCH register.
Figure 14.43. EBI TFT Vertical Porch Timing
VBPORCH
(0, 1, 2, ...)
...
LINES
VERTICAL BA..C. K PORCH
L0
...
EBI_HSYNC
VSZ
(1, 2, 3, ...)
...
L1
...
...
LVSZ
VFPORCH
(0, 1, 2, ...)
...
VERTICAL FRO...NT PORCH
...
EBI_VSYNC
VSYNC
(1, 2, 3, ...)
The active edge of the EBI_DCLK and the other TFT related signals are by default driven off the positive
edge of the internal clock. The edges of the EBI_DCLK can also be driven off the negative edge of the
internal clock by setting the SHIFTDCLK bitfield in the EBI_TFTCTRL register to 1. The Direct Drive
engine then shifts the active DCLK edge 1/2 an internal cycle into the TFTHOLD state. Effectively the
length of TFTSETUP state is increased by 1/2 an internal cycle, whereas the length of the TFTHOLD
state is decreased by 1/2 an internal cycle. SHIFTDCLK should not be set if TFTHOLD is set to zero
cycles. The effect of the SHIFTDCLK bitfield is shown in Figure 14.44 (p. 205) and Figure 14.45 (p.
205) for a setup using the falling EBI_DCLK clock as its active edge.
Figure 14.44. EBI TFT Pixel Timing: EBI_DCLK driven off Positive Edge Internal Clock
INTERNAL CLOCK
EBI_DCLK
EBI_AD[ 15:0]
PIXEL N
TFTSETUP
(0, 1, 2, ...)
TFTHOLD
(0, 1, 2, ...)
Figure 14.45. EBI TFT Pixel Timing: EBI_DCLK driven off Negative Edge Internal Clock
INTERNAL CLOCK
EBI_DCLK
EBI_AD[ 15:0]
PIXEL N
TFTSETUP
(0, 1, 2, ...)
TFTSETUPHOLD
(½ + ½)
TFTHOLD
(0, 1, 2, ...)
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
205
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