EFM32WG Datasheet, PDF (337/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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3. The application sets the Power Clamp bit in the Power and Clock Gating Control register.
4. The application sets the Reset to Power-Down Modules bit in the Power and Clock Gating Control
register.
5. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register, the core
suspends the PHY and the PHY clock stops. If USB_HCFG.ENA32KHZS is set, switch the USBC
clock to 32 kHz.
6. Enter EM2.
Host Mode Resume in EM2
Sequence of operations:
1. The resume event starts by the application waking up from EM2 (on an interrupt)
2. Switch USBC clock back to 48 MHz.
3. The application clears the Stop PHY Clock bit and the core takes the PHY back to normal mode.
The PHY clock starts up.
4. The application clears the Power Clamp bit. The core starts driving Resume signaling on the USB.
5. The application clears the Reset to Power-Down Modules bit.
6. The application programs registers in the CSR and sets the Port Resume bit in Host Port CSR (Setting
the Port Resume bit is required by the core, although Resume signaling starts earlier).
7. The application clears the Port Resume bit and the core stops driving Resume signaling.
The core is in normal operating mode.
Note
The application must insert delays of at least 2 PHY clocks between all steps in this
sequence. This requirement applies to all USB EM2 programming sequences.
Host Mode Remote Wakeup in EM2
Sequence of operations:
1. The core detects Remote Wakeup signaling on the USB. The PHY exits suspend mode and the PHY
clock restarts.
2. The core generates a Remote Wakeup Detected interrupt. The Remote Wakeup interrupt is generated
using the 32 kHz clock depending on the USB_HCFG.RESVALID (ResumeValidPeriod) programmed.
The Host Core starts resume signaling at this stage.
3. The USBC clock is switched back to normal 48 MHz clock.
4. The application clears the Stop PHY Clock bit.
5. The application clears the Power Clamp bit.
6. The application clears the Reset to Power-Down Modules bit
7. The application programs CSRs and sets the Port Resume bit. The core continues to drive Resume
signaling on the USB.
8. The application clears the Port Resume bit and the core stops driving Resume signaling.
The core enters normal operating mode.
Host Mode Session End in EM2
Sequence of operations:
1. Back up the essential registers of the core. Read and store the following core registers:
• USB_GINTMSK
• USB_GOTGCTL
• USB_DCTL
• USB_DAINTMSK
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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