EFM32WG Datasheet, PDF (564/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

Bit
Name
Reset
Enable interrupt on overflow.
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Access Description
21.5.9 RTC_FREEZE - Freeze Register
Offset
0x020
Reset
Access
Bit Position
Name
Bit
31:1
0
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
REGFREEZE
0
RW
Register Update Freeze
When set, the update of the RTC is postponed until this bit is cleared. Use this bit to update several registers simultaneously.
Value
0
1
Mode
UPDATE
FREEZE
Description
Each write access to an RTC register is updated into the Low Frequency domain as
soon as possible.
The RTC is not updated with the new written value until the freeze bit is cleared.
21.5.10 RTC_SYNCBUSY - Synchronization Busy Register
Offset
0x024
Reset
Access
Bit Position
Name
Bit
Name
Reset
Access Description
31:3
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
2
COMP1
0
R
COMP1 Register Busy
Set when the value written to COMP1 is being synchronized.
1
COMP0
0
R
COMP0 Register Busy
Set when the value written to COMP0 is being synchronized.
0
CTRL
0
R
CTRL Register Busy
Set when the value written to CTRL is being synchronized.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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