EFM32WG Datasheet, PDF (592/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

23.4 Register Map
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The offset register address is relative to the registers base address.
Offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
0x040
Name
LETIMERn_CTRL
LETIMERn_CMD
LETIMERn_STATUS
LETIMERn_CNT
LETIMERn_COMP0
LETIMERn_COMP1
LETIMERn_REP0
LETIMERn_REP1
LETIMERn_IF
LETIMERn_IFS
LETIMERn_IFC
LETIMERn_IEN
LETIMERn_FREEZE
LETIMERn_SYNCBUSY
LETIMERn_ROUTE
Type
RW
W1
R
RWH
RW
RW
RW
RW
R
W1
W1
RW
RW
R
RW
Description
Control Register
Command Register
Status Register
Counter Value Register
Compare Value Register 0
Compare Value Register 1
Repeat Counter Register 0
Repeat Counter Register 1
Interrupt Flag Register
Interrupt Flag Set Register
Interrupt Flag Clear Register
Interrupt Enable Register
Freeze Register
Synchronization Busy Register
I/O Routing Register
23.5 Register Description
23.5.1 LETIMERn_CTRL - Control Register (Async Reg)
For more information about Asynchronous Registers please see Section 5.3 (p. 21) .
Offset
0x000
Reset
Access
Bit Position
Name
Bit
31:13
12
11
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
DEBUGRUN
0
RW
Set to keep the LETIMER running in debug mode.
Debug Mode Run Enable
Value
0
1
Description
LETIMER is frozen in debug mode
LETIMER is running in debug mode
RTCC1TEN
0
RW
RTC Compare 1 Trigger Enable
Allows the LETIMER to be started on a compare match on RTC compare channel 1.
Value
0
Description
LETIMER is not affected by RTC compare channel 1
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
592
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