EFM32WG Datasheet, PDF (300/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Figure 15.23. ISOC OUT Application Flow for Periodic Transfer Interrupt Feature
N ot e:
1 . Th e( m icr o-) f r a m e n u m b e r a n d PID f ie ld a r e n ot u p d a t e d f or Pe r iod ic OUT
packet s
2 . In Pe r iod ic OUT t r a n s,f e r sa n y sh or t p a ck e t r e su lt s in a n X f e r Com p le t e
In t e r r u p t a n d d isa b le s t h e e n.d pTohinet a p p lica t ion m u st r e e n a b le t h e
e ndpoint w it h re ca lcula t e d va lue s of Xfe rSize a nd Pkt Cnt
3.
The applicat ion m ust reenable t he endpoint aft er dropped packet s for
ISOC OU
START
Intialize variables
Alloca t e a b u f f e r in t h e Syst e m M e m or y f or m u.lt ip le X f e r s
Bu f f e r size m u st b e a m u lt ip le of M a.xPk t Size
Program t he DMA address
USB_DOEPx_DMA =START Ad d r e ss of t h e D a t a M e m or y
Program Xfer_ size regist er
USB_D OEPx _TSI.ZXFERSIZ E=
XferSize Spanning across m ult iple Xfers
USB_DOEPx_TSI.Z .PKTCNT= Pr og r a m Pk t Cn t f or m u lt ip le X f e r s
Program t he Global INT STS
GINTM.SK. INCOMPLPMSK = 0
// M a sk Incom pISOCOUT Int e rrupt
Program EP Ct rl regist er t o st art t he xfer
USB_DOEPx_CTL . CNAK =1
USB_DOEPx_CTL .EPENA = 1
USB_DOEPx_CTL . SNAK = 0
USB_DOEPx_CTL .EPDIS = 0
Re- com put e XFERSIZE and
PKTCNT
Wait for USB_DOEPx_INT. XFERCOMPL int errupt and report error if t im eout expires
If USB_DOEPx_TSIZ.PKTCNT= =0
NO
YES
If USB_DOEPx_INT.PKTDRPSTS= =1
NO
If USB_DOEPx_TSIZ.XFERSIZE= =0
Received Short Packet
YES
YES
ISOC OUT Pkt Drop
End of Transfer
NO
If USB_DOEPx_TSIZ.XFERSIZE ! = 0
YES
Received Short Packet
Ret urn
NO
ERROR
Internal Data Flow
1. The application must set the Transfer Size, Packets to be received in a frame and Packet Count Fields
in the endpoint-specific registers, clear the NAK bit, and enable the endpoint to receive the data.
2. When an isochronous OUT endpoint is enabled by setting the Endpoint Enable and clearing the NAK
bits, the Even/Odd frame will be ignored by the core.
3. Once the NAK bit is cleared, the core starts receiving data and writes it to the receive FIFO, as long
as there is space in the receive FIFO. For every data packet received on the USB, the data packet
and its status are written to the receive FIFO. Every packet (maximum packet size or short packet)
written to the receive FIFO decrements the Packet Count field for that endpoint by 1.
4. When the packet count becomes 0 or when a short packet is received on the endpoint, the NAK bit
for that endpoint is set. Once the NAK bit is set, the ISOC packets are ignored and not written to
the receive FIFO.
5. After the data is written to the receive FIFO, the core’s DMA engine, reads the data from the receive
FIFO and writes it to external memory, one packet at a time per endpoint.
6. At the end of every packet write on the AHB to external memory, the transfer size for the endpoint
is decremented by the size of the written packet.
7. The OUT Data Transfer Completed pattern for an OUT endpoint is written to the receive FIFO on
one of the following conditions.
• The transfer size is 0 and the packet count is 0
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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