EFM32WG Datasheet, PDF (464/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Figure 17.16. USART SPI timing with SMSDELAY
USn _CLK
USn _CS
USn _TX
(MOSI)
X
0
1
2
3
4
5
6
7
X
USn _RX
(MISO)
X
0
1
2
3
Ordinary Sam ple Edge
4
5
6
7
X
Sam ple Edge wit h SMSDELAY
17.3.3.4 Slave Mode
When the USART is in slave mode, data transmission is not controlled by the USART, but by an external
master. The USART is therefore not able to initiate a transmission, and has no control over the number
of bytes written to the master.
The output and input to the USART are also swapped when in slave mode, making the receiver take its
input from USn_TX (MOSI) and the transmitter drive USn_RX (MISO).
To transmit data when in slave mode, the slave must load data into the transmit buffer and enable the
transmitter. The data will remain in the USART until the master starts a transmission by pulling the
USn_CS input of the slave low and transmitting data. For every frame the master transmits to the slave,
a frame is transferred from the slave to the master. After a transmission, MISO remains in the same
state as the last bit transmitted. This also applies if the master transmits to the slave and the slave TX
buffer is empty.
If the transmitter is enabled in synchronous slave mode and the master starts transmission of a frame,
the underflow interrupt flag TXUF in USARTn_IF will be set if no data is available for transmission to
the master.
If the slave needs to control its own chip select signal, this can be achieved by clearing CSPEN in the
ROUTE register. The internal chip select signal can then be controlled through CSINV in the CTRL
register. The chip select signal will be CSINV inverted, i.e. if CSINV is cleared, the chip select is active
and vice versa.
17.3.3.4.1 Synchronous Slave Setup Early
To improve speed in certain conditions by improving the setup time when running in slave mode, the
slave can be configured to set up data one half SCLK-cycle earlier, i.e. on the previous sample edge,
which, for SPI mode 0, is the falling edge. This is enabled by setting SSSEARLY in USARTn_CTRL and
can be used with all SPI masters that samples the data on the sample edge, as the SCLK propagation
delay will ensure sufficient hold time.
Note
If used together with another Energy Micro chip utilizing SMSDELAY, a very thorough
understanding of the timing is required.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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