EFM32WG Datasheet, PDF (193/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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• Command and address phase: Program the NAND Command register to the page read command
and program the NAND Address register to the required read address. This can be done via Cortex-
M4 or DMA writes to the memory mapped NAND Command and Address registers. The automatic
data access width conversions described in Section 14.3.11 (p. 185) can be used if desired to for
example automatically perform 4 consecutive address byte transactions in response to one 32-bit
word AHB write to the NAND Address register (in this case the 2 address LSBs should not be used
to map onto the NAND ALE/CLE signals).
• Data transfer phase: Wait for the NAND Flash internal data transfer phase to complete as indicated
via its ready/busy (R/B) pin. The user can use the GPIO interrupt functionality for this. The 528-byte
data is now ready for sequential transfer from the NAND Flash Data register.
• Read phase: Clear the ECC_PARITY register and start Error Code Correction (ECC) parity generation
by setting both the ECCSTART and ECCCLEAR bitfields in the EBI_CMD register to 1. Now all
subsequently transferred data to/from the NAND Flash devices is used to generate the ECC parity
code into the EBI_ECCPARITY register. Read 512 subsequent bytes of main area data from the
NAND Flash Data register via DMA transfers. This can for example be done via 32-bit word DMA
transfers (as long as the two address LSBs are not used to map onto the NAND ALE/CLE signals).
Stop ECC parity generation by setting the ECCSTOP bitfield in the EBI_CMD register to 1 so that
following transactions will not modify the parity result. Read out the final 16 bytes from the NAND
Flash spare data area.
• Error correction phase: Compare the ECC code contained in the read spare area data against the
computed ECC code from the EBI_ECCPARITY register. The user software can accept, correct, or
discard the read data according the comparison result. No automatic correction is performed.
A typical 528-byte page program sequence for an 8-bit wide NAND Flash is as follows:
• Configuration: Configure the EBI for NAND Flash support via the EBI_NANDCTRL, EBI_CTRL,
EBI_RDTIMING and EBI_WRTIMING registers.
• Command and address phase: Program the NAND Command register to command for page
programming (serial data input) and program the NAND Address register to the desired write address.
• Write phase: Clear the ECC_PARITY register and start Error Code Correction (ECC) parity generation
by setting both the ECCSTART and ECCCLEAR bitfields in the EBI_CMD register to 1. Now all
subsequently transferred data to/from the NAND Flash devices is used to generate the ECC parity
code into the EBI_ECCPARITY register. Write 512 subsequent bytes of user main data to the NAND
Flash Data register via for example DMA transfers. Stop ECC parity generation and read out the
computed ECC parity data from EBI_ECCPARITY. Write the final 16 bytes of spare data including
the computed ECC parity data bytes.
• Program phase: Write the auto program command to the NAND Flash Command register after which
the NAND Flash will indicate that it is busy via its read/busy (R/B) pin. After read/busy goes high again,
the success of the program command can be verified by programming the read status command.
14.3.15 Error Correction Code
The EBI provides provides hardware support for generation of an Error Correction Code (ECC). The used
ECC is a Hamming (Hsiao) code providing single bit error correction and double error detection (SEC-
DED). ECC can be used to detect and/or correct failing bits in a NAND Flash page. ECC generation
is enabled by setting bitfield ECCSTART in the EBI_CMD register to 1. All subsequent data traffic
to/from the memory bank specified in the BANKSEL bitfield of the EBI_NANDCTRL register is then
used for generation of the ECC into the EBI_ECCPARITY register independent of the address in that
bank. ECC generation is stopped by writing 1 to the ECCSTOP bitfield in the EBI_CMD register. The
EBI_ECCPARITY register is cleared by writing 1 to the ECCCLEAR register. The ECCACT status bit in
the EBI_STATUS register shows whether ECC generation is active or not.
The ECC computation is as shown in Figure 14.31 (p. 194) and Table 14.8 (p. 194) . Although the
table only shows the ECC generation for 8-bit data transfers, the ECC hardware also works for 16-bit
data transfers. In that case only the interpretation of the parity bits is different.
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