EFM32WG Datasheet, PDF (482/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Bit
Name
Reset
Access Description
Set to disable transmitter and release data bus directly after transmission.
13
TXBREAK
0
W
Transmit Data As Break
Set to send data as a break. Recipient will see a framing error or a break condition depending on its configuration and the value
of WDATA.
12
TXTRIAT
0
W
Set TXTRI After Transmission
Set to tristate transmitter by setting TXTRI after transmission.
11
UBRXAT
0
W
Unblock RX After Transmission
Set clear RXBLOCK after transmission, unblocking the receiver.
10:9
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
8:0
TXDATAX
0x000
W
TX Data
Use this register to write data to the USART. If TXEN is set, a transfer will be initiated at the first opportunity.
17.5.14 USARTn_TXDATA - TX Buffer Data Register
Offset
0x034
Reset
Access
Bit Position
Name
Bit
Name
Reset
Access Description
31:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
7:0
TXDATA
0x00
W
TX Data
This frame will be added to TX buffer. Only 8 LSB can be written using this register. 9th bit and control bits will be cleared.
17.5.15 USARTn_TXDOUBLEX - TX Buffer Double Data Extended Register
Offset
0x038
Reset
Access
Bit Position
Name
Bit
Name
Reset
Access Description
31
RXENAT1
0
W
Enable RX After Transmission
Set to enable reception after transmission.
30
TXDISAT1
0
W
Clear TXEN After Transmission
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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