EFM32WG Datasheet, PDF (607/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

24.4 Register Map
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The offset register address is relative to the registers base address.
Offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x038
0x03C
Name
PCNTn_CTRL
PCNTn_CMD
PCNTn_STATUS
PCNTn_CNT
PCNTn_TOP
PCNTn_TOPB
PCNTn_IF
PCNTn_IFS
PCNTn_IFC
PCNTn_IEN
PCNTn_ROUTE
PCNTn_FREEZE
PCNTn_SYNCBUSY
PCNTn_AUXCNT
PCNTn_INPUT
Type
RW
W1
R
R
R
RW
R
W1
W1
RW
RW
RW
R
RWH
RW
Description
Control Register
Command Register
Status Register
Counter Value Register
Top Value Register
Top Value Buffer Register
Interrupt Flag Register
Interrupt Flag Set Register
Interrupt Flag Clear Register
Interrupt Enable Register
I/O Routing Register
Freeze Register
Synchronization Busy Register
Auxiliary Counter Value Register
PCNT Input Register
24.5 Register Description
24.5.1 PCNTn_CTRL - Control Register (Async Reg)
For more information about Asynchronous Registers please see Section 5.3 (p. 21) .
Offset
0x000
Reset
Access
Bit Position
Name
Bit
31:16
15:14
13:12
11:10
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
AUXCNTEV
0x0
RW
Controls when the auxiliary counter counts
Selects whether the auxiliary counter responds to up-count events, down-count events or both
Value
0
1
2
3
Mode
NONE
UP
DOWN
BOTH
Description
Never counts.
Counts up on up-count events.
Counts up on down-count events.
Counts up on both up-count and down-count events.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
CNTEV
0x0
RW
Controls when the counter counts
Selects whether the regular counter responds to up-count events, down-count events or both
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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