EFM32WG Datasheet, PDF (797/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

33.4 Register Map
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The offset register address is relative to the registers base address.
Offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x040
0x044
0x048
0x04C
0x050
0x054
0x058
0x05C
0x060
0x064
0x0B4
0x0B8
0x0BC
0x0C0
0x0CC
0x0D0
0x0D4
0x0D8
Name
LCD_CTRL
LCD_DISPCTRL
LCD_SEGEN
LCD_BACTRL
LCD_STATUS
LCD_AREGA
LCD_AREGB
LCD_IF
LCD_IFS
LCD_IFC
LCD_IEN
LCD_SEGD0L
LCD_SEGD1L
LCD_SEGD2L
LCD_SEGD3L
LCD_SEGD0H
LCD_SEGD1H
LCD_SEGD2H
LCD_SEGD3H
LCD_FREEZE
LCD_SYNCBUSY
LCD_SEGD4H
LCD_SEGD5H
LCD_SEGD6H
LCD_SEGD7H
LCD_SEGD4L
LCD_SEGD5L
LCD_SEGD6L
LCD_SEGD7L
Type
RW
RW
RW
RW
R
RW
RW
R
W1
W1
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
RW
RW
RW
RW
RW
RW
RW
RW
Description
Control Register
Display Control Register
Segment Enable Register
Blink and Animation Control Register
Status Register
Animation Register A
Animation Register B
Interrupt Flag Register
Interrupt Flag Set Register
Interrupt Flag Clear Register
Interrupt Enable Register
Segment Data Low Register 0
Segment Data Low Register 1
Segment Data Low Register 2
Segment Data Low Register 3
Segment Data High Register 0
Segment Data High Register 1
Segment Data High Register 2
Segment Data High Register 3
Freeze Register
Synchronization Busy Register
Segment Data High Register 4
Segment Data High Register 5
Segment Data High Register 6
Segment Data High Register 7
Segment Data Low Register 4
Segment Data Low Register 5
Segment Data Low Register 6
Segment Data Low Register 7
33.5 Register Description
33.5.1 LCD_CTRL - Control Register (Async Reg)
For more information about Asynchronous Registers please see Section 5.3 (p. 21) .
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
797
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