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Bit
Name
Reset
Access Description
The core sets this bit when it fails to write an isochronous OUT packet into the RxFIFO because the RxFIFO does not have enough
space to accommodate a maximum packet size packet for the isochronous OUT endpoint.
13
ENUMDONE
0
RW1
Enumeration Done (device only)
The core sets this bit to indicate that speed enumeration is complete. The application must read the Device Status (USB_DSTS)
register to obtain the enumerated speed.
12
USBRST
0
RW1
USB Reset (device only)
The core sets this bit to indicate that a reset is detected on the USB.
11
USBSUSP
0
RW1
USB Suspend (device only)
The core sets this bit to indicate that a suspend was detected on the USB. The core enters the Suspended state when there is no
activity on the bus for an extended period of time.
10
ERLYSUSP
0
RW1
Early Suspend (device only)
The core sets this bit to indicate that an Idle state has been detected on the USB for 3 ms.
9:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
7
GOUTNAKEFF
0
R
Global OUT NAK Effective (device only)
Indicates that the Set Global OUT NAK bit in the Device Control register (USB_DCTL.SGOUTNAK), set by the application,
has taken effect in the core. This bit can be cleared by writing the Clear Global OUT NAK bit in the Device Control register
(USB_DCTL.CGOUTNAK).
6
GINNAKEFF
0
R
Global IN Non-periodic NAK Effective (device only)
Indicates that the Set Global Non-periodic IN NAK bit in the Device Control register (USB_DCTL.SGNPINNAK), set by the application,
has taken effect in the core. That is, the core has sampled the Global IN NAK bit set by the application. This bit can be cleared by
clearing the Clear Global Non-periodic IN NAK bit in the Device Control register (USB_DCTL.CGNPINNAK). This interrupt does not
necessarily mean that a NAK handshake is sent out on the USB. The STALL bit takes precedence over the NAK bit.
5
NPTXFEMP
1
R
Non-Periodic TxFIFO Empty (host only)
This interrupt is asserted when the Non-periodic TxFIFO is either half or completely empty, and there is space for at least one entry
to be written to the Non-periodic Transmit Request Queue. The half or completely empty status is determined by the Non-periodic
TxFIFO Empty Level bit in the Core AHB Configuration register (USB_GAHBCFG.NPTXFEMPLVL).
4
RXFLVL
0
R
RxFIFO Non-Empty (host and device)
Indicates that there is at least one packet pending to be read from the RxFIFO.
3
SOF
0
RW1
Start of Frame (host and device)
In Host mode, the core sets this bit to indicate that an SOF (FS) or Keep-Alive (LS) is transmitted on the USB. The application must
write a 1 to this bit to clear the interrupt.
In Device mode, in the core sets this bit to indicate that an SOF token has been received on the USB. The application can read the
Device Status register to get the current frame number. This interrupt is seen only when the core is operating at full-speed (FS). This
bit can be set only by the core and the application should write 1 to clear it.
2
OTGINT
0
R
OTG Interrupt (host and device)
The core sets this bit to indicate an OTG protocol event. The application must read the OTG Interrupt Status (USB_GOTGINT) register
to determine the exact event that caused this interrupt. The application must clear the appropriate status bit in the USB_GOTGINT
register to clear this bit.
1
MODEMIS
0
RW1
Mode Mismatch Interrupt (host and device)
The core sets this bit when the application is trying to access a Host mode register, when the core is operating in Device mode or when
the application accesses a Device mode register, when the core is operating in Host mode. The register access is ignored by the core
internally and does not affect the operation of the core. This bit can be set only by the core and the application should write 1 to clear it.
0
CURMOD
0
Indicates the current mode.
R
Current Mode of Operation (host and device)
Value
0
1
Mode
DEVICE
HOST
Description
Device mode.
Host mode.
15.6.14 USB_GINTMSK - Interrupt Mask Register
This register works with the Interrupt Register (USB_GINTSTS) to interrupt the application. When an
interrupt bit is masked (bit is 0), the interrupt associated with that bit is not generated. However, the
USB_GINTSTS register bit corresponding to that interrupt is still set.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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