EFM32WG Datasheet, PDF (509/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Bit
31:15
14:3
2:0
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
DIV
0x000
RW
Fractional Clock Divider
Specifies the fractional clock divider for the LEUART.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
19.5.5 LEUARTn_STARTFRAME - Start Frame Register (Async Reg)
For more information about Asynchronous Registers please see Section 5.3 (p. 21) .
Offset
0x010
Reset
Bit Position
Access
Name
Bit
Name
Reset
Access Description
31:9
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
8:0
STARTFRAME
0x000
RW
Start Frame
When a frame matching STARTFRAME is detected by the receiver, STARTF interrupt flag is set, and if SFUBRX is set, RXBLOCK
is cleared. The start-frame is be loaded into the RX buffer.
19.5.6 LEUARTn_SIGFRAME - Signal Frame Register (Async Reg)
For more information about Asynchronous Registers please see Section 5.3 (p. 21) .
Offset
0x014
Bit Position
Reset
Access
Name
Bit
Name
Reset
Access Description
31:9
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
8:0
SIGFRAME
0x000
RW
Signal Frame
When a frame matching SIGFRAME is detected by the receiver, SIGF interrupt flag is set.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
509
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