EFM32WG Datasheet, PDF (543/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

...the world's most energy friendly microcontrollers
Bit
31:11
10
9
8
7
6
5
4
3:2
1
0
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
ICBOF2
0
R
CC Channel 2 Input Capture Buffer Overflow Interrupt Flag
This bit indicates that a new capture value has pushed an unread value out of the TIMERn_CC2_CCV/TIMERn_CC2_CCVB register
pair.
ICBOF1
0
R
CC Channel 1 Input Capture Buffer Overflow Interrupt Flag
This bit indicates that a new capture value has pushed an unread value out of the TIMERn_CC1_CCV/TIMERn_CC1_CCVB register
pair.
ICBOF0
0
R
CC Channel 0 Input Capture Buffer Overflow Interrupt Flag
This bit indicates that a new capture value has pushed an unread value out of the TIMERn_CC0_CCV/TIMERn_CC0_CCVB register
pair.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
CC2
0
R
CC Channel 2 Interrupt Flag
This bit indicates that there has been an interrupt event on Compare/Capture channel 2.
CC1
0
R
CC Channel 1 Interrupt Flag
This bit indicates that there has been an interrupt event on Compare/Capture channel 1.
CC0
0
R
CC Channel 0 Interrupt Flag
This bit indicates that there has been an interrupt event on Compare/Capture channel 0.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
UF
0
R
Underflow Interrupt Flag
This bit indicates that there has been an underflow.
OF
0
R
Overflow Interrupt Flag
This bit indicates that there has been an overflow.
20.5.6 TIMERn_IFS - Interrupt Flag Set Register
Offset
0x014
Reset
Access
Bit Position
Name
Bit
31:11
10
9
8
7
6
5
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
ICBOF2
0
W1
CC Channel 2 Input Capture Buffer Overflow Interrupt Flag Set
Writing a 1 to this bit will set Compare/Capture channel 2 input capture buffer overflow interrupt flag.
ICBOF1
0
W1
CC Channel 1 Input Capture Buffer Overflow Interrupt Flag Set
Writing a 1 to this bit will set Compare/Capture channel 1 input capture buffer overflow interrupt flag.
ICBOF0
0
W1
CC Channel 0 Input Capture Buffer Overflow Interrupt Flag Set
Writing a 1 to this bit will set Compare/Capture channel 0 input capture buffer overflow interrupt flag.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
CC2
0
W1
CC Channel 2 Interrupt Flag Set
Writing a 1 to this bit will set Compare/Capture channel 2 interrupt flag.
CC1
0
W1
CC Channel 1 Interrupt Flag Set
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
543
www.energymicro.com