EFM32WG Datasheet, PDF (329/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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The application must wait until the TXFFLSH bit and the RXFFLSH bits are cleared before performing
any operation on the core.
15.4.7.1.2 Host Mode
Considerations for allocating data RAM for Host Mode FIFOs are listed here:
Receive FIFO RAM allocation:
Status information is written to the FIFO along with each received packet. Therefore, a minimum space of
(Largest Packet Size / 4) + 2 must be allotted to receive packets. If a high-bandwidth channel is enabled,
or multiple isochronous channels are enabled, then at least two (Largest Packet Size / 4) + 2 spaces
must be allotted to receive back-to-back packets. Typically, two (Largest Packet Size / 4) + 2 spaces are
recommended so that when the previous packet is being transferred to AHB, the USB can receive the
subsequent packet. If AHB latency is high, you must allocate enough space to receive multiple packets.
Along with each host channel’s last packet, information on transfer complete status and channel halted
is also pushed to the FIFO. So two locations must be allocated for this.
For handling NAK in DMA mode, the application must determine the number of Control/Bulk OUT
endpoint data that must fit into the TX_FIFO at the same instant. Based on this, one location each is
required for Control/Bulk OUT endpoints.
For example, when the host addresses one Control OUT endpoint and three Bulk OUT endpoints, and
all these must fit into the non-periodic TX_FIFO at the same time, then four extra locations are required
in the RX FIFO to store the rewind status information for each of these endpoints.
Transmit FIFO RAM allocation
The minimum amount of RAM required for the Host Non-periodic Transmit FIFO is the largest maximum
packet size among all supported non-periodic OUT channels.
More space allocated in the Transmit Non-periodic FIFO results in better performance on the USB and
can hide AHB latencies. Typically, two Largest Packet Sizes’ worth of space is recommended, so that
when the current packet is under transfer to the USB, the AHB can get the next packet. If the AHB
latency is large, then you must allocate enough space to buffer multiple packets.
The minimum amount of RAM required for Host periodic Transmit FIFO is the largest maximum packet
size among all supported periodic OUT channels. If there is at lease one High Bandwidth Isochronous
OUT endpoint, then the space must be at least two times the maximum packet size of that channel.
15.4.7.1.2.1 Internal Register Storage Space Allocation
When operating in DMA mode, the DMA address register for each host channel (USB_HCx_DMAADDR)
is stored in the FIFO RAM. One location for each channel must be reserved for this.
Table 15.4.
FIFO Name
Receive Data FIFO
Non-periodic Transmit FIFO
IN Endpoint Transmit FIFO
Data RAM Size
rx_fifo_size
tx_fifo_size[0]
tx_fifo_size[1]
With this information, the following registers must be programmed:
1. Receive FIFO Size Register (USB_GRXFSIZ)
• USB_GRXFSIZ.RXFDEP = rx_fifo_size;
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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