EFM32WG Datasheet, PDF (801/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Bit
17:16
15:9
8
7
6:5
4:3
2
1
0
Name
Reset
Access Description
FCPRESC
0x0
RW
Frame Counter Prescaler
These bits controls the prescaling value for the Frame Counter input clock.
Value
0
1
2
3
Reserved
Mode
DIV1
DIV2
DIV4
DIV8
Description
CLK_FC = CLK_FRAME / 1
CLK_FC = CLK_FRAME / 2
CLK_FC = CLK_FRAME / 4
CLK_FC = CLK_FRAME / 8
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
FCEN
0
RW
Frame Counter Enable
When this bit is set, the frame counter is enabled.
ALOGSEL
0
RW
Animate Logic Function Select
When this bit is set, the animation registers are AND'ed together. When this bit is cleared, the animation registers are OR'ed together.
Value
0
1
Mode
AND
OR
Description
AREGA and AREGB AND'ed
AREGA and AREGB OR'ed
AREGBSC
0x0
RW
Animate Register B Shift Control
These bits controls the shift operation that is performed on Animation register B.
Value
0
1
2
Mode
NOSHIFT
SHIFTLEFT
SHIFTRIGHT
Description
No Shift operation on Animation Register B
Animation Register B is shifted left
Animation Register B is shifted right
AREGASC
0x0
RW
Animate Register A Shift Control
These bits controls the shift operation that is performed on Animation register A.
Value
0
1
2
Mode
NOSHIFT
SHIFTLEFT
SHIFTRIGHT
Description
No Shift operation on Animation Register A
Animation Register A is shifted left
Animation Register A is shifted right
AEN
0
RW
Animation Enable
When this bit is set, the animate function is enabled.
BLANK
0
RW
Blank Display
When this bit is set, all segment output waveforms are configured to blank the LCD display. The Segment Data Registers are not
affected when writing this bit.
Value
0
1
Description
Display is not "blanked"
Display is "blanked"
BLINKEN
0
RW
Blink Enable
When this bit is set, the Blink function is enabled. Every "ON" segment will alternate between on and off at every Frame Counter Event.
33.5.5 LCD_STATUS - Status Register
Offset
0x010
Reset
Access
Bit Position
Name
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
801
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