English
Language : 

EFM32WG Datasheet, PDF (362/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.
...the world's most energy friendly microcontrollers
Bit
Name
Reset
Access Description
Set to 1 to unmask USBRST interrupt.
11
USBSUSPMSK
0
RW
USB Suspend Mask (device only)
Set to 1 to unmask USBSUSP interrupt.
10
ERLYSUSPMSK
0
RW
Early Suspend Mask (device only)
Set to 1 to unmask ERLYSUSP interrupt.
9:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
7
GOUTNAKEFFMSK
0
RW
Global OUT NAK Effective Mask (device only)
Set to 1 to unmask GOUTNAKEFF interrupt.
6
GINNAKEFFMSK
0
RW
Global Non-periodic IN NAK Effective Mask (device only)
Set to 1 to unmask GINNAKEFF interrupt.
5
NPTXFEMPMSK
0
RW
Non-Periodic TxFIFO Empty Mask (host only)
Set to 1 to unmask NPTXFEMP interrupt.
4
RXFLVLMSK
0
RW
Receive FIFO Non-Empty Mask (host and device)
Set to 1 to unmask RXFLVL interrupt.
3
SOFMSK
0
RW
Start of Frame Mask (host and device)
Set to 1 to unmask SOF interrupt.
2
OTGINTMSK
0
RW
OTG Interrupt Mask (host and device)
Set to 1 to unmask OTGINT interrupt.
1
MODEMISMSK
0
RW
Mode Mismatch Interrupt Mask (host and device)
Set to 1 to unmask MODEMIS interrupt.
0
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
15.6.15 USB_GRXSTSR - Receive Status Debug Read Register
A read to the Receive Status Debug Read register returns the contents of the top of the Receive FIFO.
The receive status contents must be interpreted differently in Host and Device modes. The core ignores
the receive status pop/read when the receive FIFO is empty and returns a value of 0x00000000. The
application must only pop the Receive Status FIFO when the Receive FIFO Non-Empty bit of the Core
Interrupt register (USB_GINTSTS.RXFLVL) is asserted.
Offset
0x3C01C
Bit Position
Reset
Access
Name
Bit
31:28
27:24
23:21
20:17
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
FN
0x0
R
Frame Number (device only)
This is the least significant 4 bits of the Frame number in which the packet is received on the USB.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
PKTSTS
0x0
R
Packet Status (host or device)
Indicates the status of the received packet.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
362
www.energymicro.com