EFM32WG Datasheet, PDF (395/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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15.6.60 USB_DOEP0CTL - Device OUT Endpoint 0 Control Register
The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
Offset
0x3CB00
Reset
Access
Bit Position
Name
Bit
31
30
29:28
27
26
25:22
21
20
19:18
17
16
15
14:2
1:0
Name
Reset
Access Description
EPENA
0
RW1
Endpoint Enable
In DMA mode this bit indicates that the application has allocated the memory to start receiving data from the USB. The core clears
this bit before setting any of the following interrupts on this endpoint: SETUP Phase Done, Endpoint Disabled, Transfer Completed.
In DMA mode, this bit must be set for the core to transfer SETUP data packets into memory.
EPDIS
0
R
Endpoint Disable
This bit is always 0. The application cannot disable control OUT endpoint 0.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
SNAK
0
W1
Set NAK
A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes
on an endpoint. The core can also set bit on a Transfer Completed interrupt, or after a SETUP is received on the endpoint.
CNAK
0
W1
Clear NAK
A write to this bit clears the NAK bit for the endpoint.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
STALL
0
RW1
Handshake
The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit or Global
OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's setting, the core always responds to SETUP
data packets with an ACK handshake.
SNP
0
RW
Snoop Mode
This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before
transferring them to application memory.
EPTYPE
0x0
R
Endpoint Type
Hardcoded to 0. Endpoint 0 is always a control endpoint.
NAKSTS
0
R
NAK Status
When this bit is 0 the core is transmitting non-NAK handshakes based on the FIFO status. When this bit is 1 the core is transmitting
NAK handshakes on this endpoint. When either the application or the core sets this bit, the core stops receiving data, even if there
is space in the RxFIFO to accommodate the incoming packet. Irrespective of this bit's setting, the core always responds to SETUP
data packets with an ACK handshake.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
USBACTEP
1
R
USB Active Endpoint
This bit is always 1, indicating that a control endpoint 0 is always active in all configurations and interfaces.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
MPS
0x0
R
Maximum Packet Size
The maximum packet size for control OUT endpoint 0 is the same as what is programmed in control IN Endpoint 0.
Value
0
1
2
Mode
64B
32B
16B
Description
64 bytes.
32 bytes.
16 bytes.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
395
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