EFM32WG Datasheet, PDF (416/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

...the world's most energy friendly microcontrollers
Worst case consequences for an address match while disabling slave or changing configuration is that
the slave may end up in an undefined state. To reset the slave back to a known state, the EN bit in
I2Cn_CTRL must be reset. This should be done regardless of whether the slave is going to be re-enabled
or not.
16.3.4 Clock Generation
The SCL signal generated by the I²C master determines the maximum transmission rate on the bus.
The clock is generated as a division of the peripheral clock, and is given by Equation 16.2 (p. 416) :
I²C Maximum Transmission Rate
f_SCL = f_HFPERCLK/(((N_low + N_high) x (DIV + 1)) + 4),
(16.2)
N_low and N_high specify the number of prescaled clock cycles in the low and high periods of the clock
signal respectively. The worst case low and high periods of the signal are:
I²C High and Low Cycles Equations
T_high >= (N_high x (DIV + 1) + 3)/f_HFPERCLK,
T_low >= (N_low x (DIV + 1) + 3)/f_HFPERCLK.
(16.3)
The values of N_low and N_high and thus the ratio between the high and low parts of the clock signal is
controlled by CLHR in the I2Cn_CTRL register. The available modes are summarized in Table 16.2 (p.
416) along with the highest I²C-bus frequencies in the given modes that can be achieved without
violating the timing specifications of the I²C-bus. The frequencies are calculated taking the maximum
allowed rise and fall times of SDA and SCL into account. Higher frequencies may be achieved in
practice. The 3 extra cycles are synchronization, and must be taken into consideration when DIV in the
I2Cn_CLKDIV register has a low value.
Note
DIV must be 1 or higher when the slave is enabled.
Table 16.2. I²C Clock Mode Examples
Mode
CLKDIV
STANDARD 0
ASYMMETRIC 0
FAST
0
STANDARD 1
ASYMMETRIC 1
FAST
1
STANDARD 2
ASYMMETRIC 2
FAST
2
CLHR
0
1
2
0
1
2
0
1
2
SCL high
cycles / SCL
low cycles
7:7
9:6
14:9
11:11
15:9
25:15
15:15
21:12
36:21
Sm max
frequency
93 kHz
88 kHz
86 kHz
93 kHz
83 kHz
83 kHz
93 kHz
81 kHz
82 kHz
Fm max
frequency
312 kHz
361 kHz
365 kHz
312 kHz
373 kHz
373 kHz
312 kHz
378 kHz
376 kHz
Fm+ max
frequency
806 kHz
931 kHz
942 kHz
806 kHz
961 kHz
961 kHz
806 kHz
974 kHz
969 kHz
16.3.5 Arbitration
Arbitration is enabled by default, but can be disabled by setting the ARBDIS bit in I2Cn_CTRL. When
arbitration is enabled, the value on SDA is sensed every time the I²C module attempts to change its
value. If the sensed value is different than the value the I²C module tried to output, it is interpreted as a
simultaneous transmission by another device, and that the I²C module has lost arbitration.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
416
www.energymicro.com