EFM32WG Datasheet, PDF (413/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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The GPIO drive strength can be used to control slew rate.
Note
If V_dd drops below the voltage on SCL and SDA lines, the MCU could become back
powered and pull the SCL and SDA lines low.
16.3.1.1 START and STOP Conditions
START and STOP conditions are used to initiate and stop transactions on the I²C-bus. All transactions on
the bus begin with a START condition (S) and end with a STOP condition (P). As shown in Figure 16.3 (p.
413) , a START condition is generated by pulling the SDA line low while SCL is high, and a STOP
condition is generated by pulling the SDA line high while SCL is high.
Figure 16.3. I²C START and STOP Conditions
SDA
SCL
S
START condit ion
P
STOP condit ion
The START and STOP conditions are easily identifiable bus events as they are the only conditions on
the bus where a transition is allowed on SDA while SCL is high. During the actual data transmission, SDA
is only allowed to change while SCL is low, and must be stable while SCL is high. One bit is transferred
per clock pulse on the I²C-bus as shown in Figure 16.2 (p. 412) .
Figure 16.4. I²C Bit Transfer on I²C-Bus
SDA
SCL
Data change
allowed
Data stable
Data change
allowed
16.3.1.2 Bus Transfer
When a master wants to initiate a transfer on the bus, it waits until the bus is idle and transmits a START
condition on the bus. The master then transmits the address of the slave it wishes to interact with and
a single R/W bit telling whether it wishes to read from the slave (R/W bit set to 1) or write to the slave
(R/W bit set to 0).
After the 7-bit address and the R/W bit, the master releases the bus, allowing the slave to acknowledge
the request. During the next bit-period, the slave pulls SDA low (ACK) if it acknowledges the request,
or keeps it high if it does not acknowledge it (NACK).
Following the address acknowledge, either the slave or master transmits data, depending on the value
of the R/W bit. After every 8 bits (one byte) transmitted on the SDA line, the transmitter releases the
line to allow the receiver to transmit an ACK or a NACK. Both the data and the address are transmitted
with the most significant bit first.
The number of bytes in a bus transfer is unrestricted. The master ends the transmission after a (N)ACK
by sending a STOP condition on the bus. After a STOP condition, any master wishing to initiate a transfer
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
413
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