EFM32WG Datasheet, PDF (613/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

Bit
Name
Value
1
2
3
7:0
Reserved
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Mode
LOC1
LOC2
LOC3
Reset
Access Description
Description
Location 1
Location 2
Location 3
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
24.5.12 PCNTn_FREEZE - Freeze Register
Offset
0x02C
Reset
Access
Bit Position
Name
Bit
31:1
0
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
REGFREEZE
0
RW
Register Update Freeze
When set, the update of the PCNT clock domain is postponed until this bit is cleared. Use this bit to update several registers
simultaneously.
Value
0
1
Mode
UPDATE
FREEZE
Description
Each write access to a PCNT register is updated into the Low Frequency domain as
soon as possible.
The PCNT clock domain is not updated with the new written value.
24.5.13 PCNTn_SYNCBUSY - Synchronization Busy Register
Offset
0x030
Reset
Access
Bit Position
Name
Bit
Name
Reset
Access Description
31:3
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
2
TOPB
0
R
TOPB Register Busy
Set when the value written to TOPB is being synchronized.
1
CMD
0
R
CMD Register Busy
Set when the value written to CMD is being synchronized.
0
CTRL
0
R
CTRL Register Busy
Set when the value written to CTRL is being synchronized.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
613
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