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15.4.3.6.14 Isochronous IN Transactions in Slave Mode
To initialize the core after power-on reset, the application must follow the sequence in Overview:
Programming the Core (p. 246) . Before it can communicate with the connected device, it must
initialize a channel as described in Channel Initialization (p. 252) . See Figure 15.10 (p. 256) and
Figure 15.11 (p. 256) for read or write data to and from the FIFO in Slave mode.
A typical isochronous IN operation in Slave mode is shown in Figure 15.17 (p. 276) . See channel 2
(ch_2). The assumptions are:
• The application is attempting to receive one packet (up to 1 maximum packet size) in every frame
starting with the next odd frame. (transfer size = 1,024 bytes).
• The receive FIFO can hold at least one maximum-packet-size packet and two status DWORDs per
packet (1,031 bytes for FS).
• Periodic Request Queue depth = 4.
15.4.3.6.14.1 Normal Isochronous IN Operation
The sequence of operations in Figure 15.17 (p. 276) (channel 2) is as follows:
1. Initialize channel 2 as explained in Channel Initialization (p. 252) . The application must set the
USB_HC2_CHAR.ODDFRM bit.
2. Set the USB_HC2_CHAR.CHENA bit to write an IN request to the Periodic Request Queue. For a
high-bandwidth isochronous transfer, the application must write the USB_HC2_CHAR register MC
(maximum number of expected packets in the next frame) times before switching to another channel.
3. The host writes an IN request to the Periodic Request Queue for each USB_HC2_CHAR register
write with the CHENA bit set.
4. The host attempts to send an IN token in the next odd frame.
5. As soon as the IN packet is received and written to the receive FIFO, the host generates an RXFLVL
interrupt.
6. In response to the RXFLVL interrupt, read the received packet status to determine the number of bytes
received, then read the receive FIFO accordingly. The application must mask the RXFLVL interrupt
before reading the receive FIFO, and unmask it after reading the entire packet.
7. The core generates an RXFLVL interrupt for the transfer completion status entry in the receive FIFO.
This time, the application must read and ignore the receive packet status when the receive packet
status is not an IN data packet (USB_GRXSTSR.PKTSTS != 0b0010).
8. The core generates an XFERCOMPL interrupt as soon as the receive packet status is read.
9. In response to the XFERCOMPL interrupt, read the USB_HC2_TSIZ.PKTCNT field. If
USB_HC2_TSIZ.PKTCNT != 0, disable the channel (as explained in Halting a Channel (p. 253)
) before re-initializing the channel for the next transfer, if any. If USB_HC2_TSIZ.PKTCNT ==
0, reinitialize the channel for the next transfer. This time, the application must reset the
USB_HC2_CHAR.ODDFRM bit.
15.4.3.6.14.2 Handling Interrupts
The channel-specific interrupt service routine for an isochronous IN transaction in Slave mode is as
follows.
Isochronous IN
Unmask (XACTERR/XFERCOMPL/FRMOVRUN/BBLERR)
if (XFERCOMPL or FRMOVRUN)
{
if (XFERCOMPL and (USB_HCx_TSIZ.PKTCNT == 0))
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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